VSC7130RC(2000) Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC7130RC
(Rev.:2000)

Dual Repeater/Retimer for Fibre Channel and Gigabit Ethernet

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Dual Repeater/Retimer

for Fibre Channel and Gigabit Ethernet

Advance Product Information

VSC7130

Please refer to the “VSC7130 User’s Manual” for a more complete description of the performance monitor-

ing capabilities and associated register controls.

Two-Wire Interface

An industry-standard Two-Wire Interface is provided to allow user access to internal control and status.

Use of the interface is optional. SCL is the serial interface clock running at up to 400 KHz when used with

readily available microcontrollers. SDA is a bidirectional data signal. A4 and A3 selects the group address of

the device while A2-A0 set the address. TWI and TWO are used to serially configure the address of daisy-

chained devices in order to accommodate large numbers of devices on each Two-Wire Interface link. INT# is

an open drain output used to signal an interruptible event to the microcontroller.

Please refer to the “VSC7130 User’s Manual” for a more complete description of this interface, including

timing diagrams.

Proprietary Interface

If higher performance than 400KHz is required, a proprietary mode may be used. In this mode, the SCL

clock can operate at a maximum speed of 6.25 MHz. Due to the speed of this link, significant electrical limita-

tions may be placed on the link which will restrict trace lengths, the number of daisy-chained devices and the

use of multiple masters.

The Verilog code for the Master Controller in proprietary mode will be made available to customers in

order to ensure compatibility. This Master Controller core is designed to use either a 25 MHz or a 50 MHz

clock to generate a 6.25 MHz SCL clock frequency with a 25% high, 75% low duty cycle (1 clock high, 3

clocks low at 25 MHz). Slower clock frequencies are also allowable.

When using the Proprietary High-Speed mode of the Two-Wire Interface, all other interface functionality is

identical to the standard Two-Wire Interface with the exception that the interface timing has changed.

Interrupt Circuitry

Interrupts are available only when the Two-Wire Interface is used otherwise INT# will be disabled. The

INT# output is open-drain so an external pull-up resistor is needed to allow the output to achieve a valid TTL or

CMOS HIGH level. Multiple INT# outputs can be wire ORed together. INT# is a glitchless signal which is

synchronized to divide-by-32 REFO clock. The output of the interrupt controller prior to the output buffer is

readable in INTOUT, CHIPS bit 2.

The VSC7130 is capable of managing several different kinds of internal interrupt conditions. Each inter-

rupt source can be enabled independently using the registers accessible via the Two-Wire Interface. When an

enabled interrupt event occurs, the open-drain INT# output will be asserted LOW and will stay LOW until the

interrupt is cleared. The register address corresponding to the highest priority pending interrupt can be read

from the ISR register (address F8h). This provides a relatively fast means for determining the source of the

interrupt with a single register read operation.

Please refer to the “VSC7130 User’s Manual” for a more complete description of the interrupt controller

and its associated register controls.

Page 10

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52297-0, Rev. 2.3

1/17/00

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