CY3688 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY3688 Datasheet PDF : 11 Pages
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A. Appendix
A.1 TX3 DVK Board Schematic
8
7
6
5
4
3
2
1
EDGE CONN/ 24PIN_QFN CONN/ USB CONNECTIONS
F
VIOR
VDD
VDDR
VIO
TP2
TP4
TP5
VIOR
TP6
R7
R13
F
1 OHM
1
2
1 OHM
1
2
VBATT
C27
2.2UF
C8
0.1UF
C9
0.01UF
VIO
C24
0.1UF
C25
0.01UF
VDD
C10
0.1UF
C11
0.01UF
C12
0.1UF
C13
0.01UF
C28
0.1UF
C29
0.01UF
2D8< 2B5< OUT
CS_N
J4
JUMP3_100MIL
11
22
33
VIOR
R27
E
2B8< 2B1< BI
2D1< 2B8< BI
2B8< 2B3< BI
2D1< 2B8< BI
2B8< 2B3< BI
2D3< 2B6< BI
2B6< 2B1< BI
2D3< 2B6< BI
U1
VBATT
DATA0
22 R15
1
2
24_PIN_QFN
4 DATA0
VBATT0_2
VDD
24
DATA1
22 R16
1
2
5 DATA1
VIO
VCC_3 3
DATA2 22 R10
1
2
6 DATA2
VCC_19 19
DATA3
1
22 R11
2
DATA4
1
R17
22
2
8 DATA3
9 DATA4
DATA5 1
22
R20
2
11
DATA5
DATA6 R18
22
1
2
12 DATA6
VIO 10
DIR 15
NXT 17
CLOCK 14
22 R22
1
2 DIR
NXT 22 R25
1
2
1
22 R23
2
CLOCK
DATA7 1
22
R19
2
13
DATA7
DP 22
2 NC
DM 23
3D7< IN
VBUS
R21
2D1< OUT
OUT 2C6< 2C1<
OUT 2C6< 2C3<
OUT 2C6< 2B5<
D4
VBUS_OUT 1
2
SOD-523
USB_DP
USB_DM
R24
2E4< 2B5< IN CS_N
2B5< 2B1< IN STP
2E4< 2B5< IN RESET_N
7 CS_N
16 STP
18 RESET_N
XI 21
XO 20
VSSBATT0_2
1
XIN
XOUT
IN 2C8>
OUT 2C6<
1 TP7
2E4< 2B5< OUT
U2
1 VBUS
3 DP
2 DM
4 GND
5 S1
6 S2
787780
J5
JUMP3_100MIL
11
RESET_N 2 2
33
VIOR
U5
VIOR
R28
2 1Y
4 2Y
6 3Y
8 4Y
10 5Y
12 6Y
1A 1
2A 3
3A 5
4A 9
5A 11
6A 13
2D8< 2B6< BI
2E8< 2B6< BI
DATA7
DATA5
D
R1
GND_SHLD
C3
OUT 3B2< 3B3< 4C2<
4.7 NF 250 V
VDDR
R5
ZERO
1
2
OSC1
4 VCC OUTPUT 3
1 NC
GND 2
R6
33
1
2
XIN
OUT 2D6<
C1 VCC1_103_OSC
0.01UF
C
VDD
J6
HEADER2
1
2
J7
HEADER2
1
2
VIO
J8
HEADER2
1
2
J9
HEADER2
1
2
R26
200
1
2
VDDR
VDDR
2E6< 2B6< IN
NXT
J2
2E8< 2B1< IN
DATA0
HEADER_10X2
11
11 11
DATA5
IN 2D3< 2E8<
22
12 12
2E8< 2D1< IN
DATA1
33
13 13
DATA6
IN 2B1< 2D8<
44
14 14
2E8< 2B3< IN
DATA2
55
15 15
DATA7
IN 2D3< 2D8<
B
66
16 16
2E8< 2D1< IN
DATA3
77
17 17
DIR
IN 2C1< 2E6<
88
18 18
2E8< 2B3< IN
DATA4
99
19 19
NXT
IN 2C3< 2E6<
10 10
20 20
2E4< 2D8< IN
2E4< 2D8< IN
2E6< 2B1< IN
2D8< 2B1< IN
RESET_N
CS_N
CLOCK
STP
J14
HEADER_10X2
11
11 11
22
12 12
33
13 13
44
14 14
55
15 15
66
16 16
77
17 17
88
18 18
99
19 19
10 10
20 20
VBATT
VDD
VIO
2E8< 2B8< BI
2E8< 2B8< BI
VIOR
DATA4
DATA2
J1
1 GPIOO
3 GPI02
5 GPI04
7 GPIO7
9 GND_9
11 GPIO9
13 GND_13
15 SPKR_L
17 RESET
19 RESERVED_19
21 GND_21
23 RESERVED_23
25 RESERVED_25
27 GND_27
29 GPIO3
31 DATA7
33 DATA5
35 GND_35
37 RESERVED_37
39 GND_39
41 RESERVED_41
43 GND_43
45 SPKR_MIC
47 VBUSIN
49 DCPSNT_N
51 GND_51
53 GND_53
55 RESERVED_55
57 VDD_57
59 RESERVED_59
61 GPIO1O
63 GPIO12
65 GND_65
67 RESERVED_67
69 VDD_69
71 NXT
73 GND_73
75 RESERVED_75
77 RESERVED_77
79 RESERVED_79
81 VIO_81
83 DATA4
85 DATA2
87 VIO_87
89 RESERVED_89
91 RESERVED_91
93 RESERVED_93
95 GND_95
97 RESERVED_97
99 RESERVED_99
EDGE CONNECTOR
GND_2
GND_4
GPIO5
VDD_8
RESERVED_10
GPIO11
RESERVED_14
VDD_16
RESERVED_18
RESERVED_20
RESERVED_22
GND_24
GPIO1
VBUS_OUT
RESERVED_30
GND_32
DATA3
DATA1
VIO_38
RESERVED_40
RESERVED_42
RESERVED_44
GND_46
RESERVED_48
GPIO13
SYS_CLK
GND_54
GPIO6
GPIO8
RESERVED_60
GND_62
RESERVED_64
RESERVED_66
GND_68
DIR
RESERVED_72
RESERVED_74
GND_76
GPIO14
GND_80
DATA6
GND_84
DATA0
RESERVED_88
CLOCK
GND_92
RESERVED_94
STP
RESERVED_98
PSU_SHD_N
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
VDDR
VDDR
E
VBUS_OUT
VIOR
DATA3
DATA1
IN 2E6<
BI 2B8< 2E8<
BI 2B8< 2E8<
D
DIR
C
IN 2B6< 2E6<
DATA6
DATA0
CLOCK
STP
BI 2B6< 2D8<
BI 2B8< 2E8<
IN
B
OUT 2B5< 2D8<
DRAWING TITLE
A
CYPRESS
TX3_DVK_BOARD
A
SEMICONDUCTOR
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
SIZE
1 CC REV.
DATE.
Thu Mar 27 17:21:28 2008
TO CYPRESS SEMICONDUCTOR. USE OR DISCLOSURE
WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF
CYPRESS IS EXPRESSLY FORBIDDEN.
COPYRIGHT (C) CYPRESS 2002
<ENGINEER>
ENGINEER <ENGINEER2>
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CY3688 MoBL-USB™ TX2UL Development Kit Guide, Doc. # 001-46448 Rev. *C
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