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LTC4440IMS8E Просмотр технического описания (PDF) - Linear Technology

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производитель
LTC4440IMS8E
Linear
Linear Technology Linear
LTC4440IMS8E Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LTC4440
PI FU CTIO S
Exposed Pad MS8E Package
INP (Pin 1): Input Signal. TTL/CMOS compatible input
referenced to GND (Pin 2).
GND (Pins 2, 4): Chip Ground.
VCC (Pin 3): Chip Supply. This pin powers the internal low
side circuitry. A low ESR ceramic bypass capacitor should
be tied between this pin and the GND pin (Pin 2).
NC (Pin 5): No Connect. No connection required. For
convenience, this pin may be tied to Pin 6 (BOOST) on the
application board.
BOOST (Pin 6): High Side Bootstrapped Supply. An exter-
nal capacitor should be tied between this pin and TS
(Pin 8). Normally, a bootstrap diode is connected between
VCC (Pin 3) and this pin. Voltage swing at this pin is from
VCC – VD to VIN + VCC – VD, where VD is the forward voltage
drop of the bootstrap diode.
TG (Pin 7): High Current Gate Driver Output (Top Gate).
This pin swings between TS and BOOST.
TS (Pin 8): Top (High Side) Source Connection.
Exposed Pad (Pin 9): Ground. Must be electrically con-
nected to Pins 2 and 4 and soldered to PCB ground for
optimum thermal performance.
BLOCK DIAGRA
8V TO 15V
VCC UNDERVOLTAGE
LOCKOUT
GND
INP
HIGH SIDE
UNDERVOLTAGE
LOCKOUT
BOOST
LEVEL SHIFTER
GND
TS
BOOST
TG
TS
WU
W
TI I G DIAGRA
INPUT (INP)
OUTPUT (TG)
INPUT RISE/FALL TIME < 10ns
VIH
VIL
tr
tPLH
tf
tPHL
90%
10%
4440 TD
6
VIN
UP TO 80V,
TRANSIENT
UP TO 100V
4440 BD
4440f

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