CY8C4125FNI-483(T) Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CY8C4125FNI-483(T)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 4: PSoC 4100 Family

Datasheet

Two Opamps (CTBm Block)

PSoC 4100 has two opamps with Comparator modes which

allow most common analog functions to be performed on-chip

eliminating external components; PGAs, voltage buffers, filters,

trans-impedance amplifiers, and other functions can be realized

with external passives saving power, cost, and space. The

on-chip opamps are designed with enough bandwidth to drive

the S/H circuit of the ADC without requiring external buffering.

Temperature Sensor

PSoC 4100 has one on-chip temperature sensor This consists

of a diode, which is biased by a current source that can be

disabled to save power. The temperature sensor is connected to

the ADC, which digitizes the reading and produces a temper-

ature value using Cypress supplied software that includes

calibration and linearization.

Low-power Comparators

PSoC 4100 has a pair of low-power comparators, which can also

operate in the Deep Sleep and Hibernate modes. This allows the

analog system blocks to be disabled while retaining the ability to

monitor external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid metasta-

bility unless operating in an asynchronous power mode

(Hibernate) where the system wake-up circuit is activated by a

comparator switch event.

Fixed Function Digital

Timer/Counter/PWM Block (TCPWM)

The TCPWM block consists of four 16-bit counters with

user-programmable period length. There is a Capture register to

record the count value at the time of an event (which may be an

I/O event), a period register which is used to either stop or

auto-reload the counter when its count is equal to the period

register, and compare registers to generate compare value

signals which are used as PWM duty cycle outputs. The block

also provides true and complementary outputs with program-

mable offset between them to allow use as deadband program-

mable complementary PWM outputs. It also has a Kill input to

force outputs to a predetermined state; for example, this is used

in motor drive systems when an overcurrent state is indicated

and the PWMs driving the FETs need to be shut off immediately

with no time for software intervention.

Serial Communication Blocks (SCB)

The PSoC 4100 has two SCBs, which can each implement an

I2C, UART, or SPI interface.

I2C Mode: The hardware I2C block implements a full

multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. The FIFO

mode is available in all channels and is very useful in the

absence of DMA.

The I2C peripheral is compatible with the I2C Standard-mode,

Fast-mode, and Fast-Mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204). The I2C bus

I/O is implemented with GPIO in open-drain modes. The I2C bus

uses open-drain drivers for clock and data with pull-up resistors

on the bus for clock and data connected to all nodes. The

required Rise and Fall times for different I2C speeds are

guaranteed by using appropriate pull-up resistor values

depending on VDD, Bus Capacitance, and resistor tolerance.

For detailed information on how to calculate the optimum pull-up

resistor value for your design, refer to the UM10204 I2C bus

specification and user manual (the latest revision is available at

www.nxp.com).

PSoC 4100 is not completely compliant with the I2C spec in the

following respects:

■ GPIO cells are not overvoltage-tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

I2C system.

■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of

0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a

VOL maximum of 0.6 V.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the Bus Load.

■ When the SCB is an I2C master, it interposes an IDLE state

between NACK and Repeated Start; the I2C spec defines Bus

free as following a Stop condition so other Active Masters do

not intervene but a Master that has just become activated may

start an Arbitration cycle.

■ When the SCB is in I2C slave mode, and Address Match on

External Clock is enabled (EC_AM = 1) along with operation in

the internally clocked mode (EC_OP = 0), then its I2C address

must be even.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(essentially adds a start pulse used to synchronize SPI Codecs),

and National Microwire (half-duplex form of SPI). The SPI block

can use the FIFO.

Document Number: 001-87220 Rev. *J

Page 7 of 43

Share Link: