CY7C1061DV18-15BV1XI Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1061DV18-15BV1XI

16-Mbit (1M × 16) Static RAM

Cypress Semiconductor 

CY7C1061DV18

Capacitance

Parameter [2]

Description

CIN

COUT

Input capacitance

I/O capacitance

Thermal Resistance

Parameter [2]

Description

JA

Thermal resistance

(junction to ambient)

JC

Thermal resistance

(junction to case)

Test Conditions

TA = 25 C, f = 1 MHz, VCC = 1.8 V.

TSOP II Unit

6

pF

8

pF

Test Conditions

Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit

board

TSOP II

24.18

5.40

Unit

C/W

C/W

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms [3]

OUTPUT

50

VTH = VDD/2

1.8V

R1 1667

Z0 = 50

30 pF* * Capacitive Load consists of all com-

OUTPUT

ponents of the test environment.

5 pF*

(a)

1.8V

ALL INPUT PULSES

90%

90%

INCLUDING

JIG AND

SCOPE (b)

GND

10%

10%

Rise time > 1 V/ns

(c)

Fall time:

> 1 V/ns

R2

1538

Notes

2. Tested initially and after any design or process changes that may affect these parameters.

3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (1.5 V). 150s (tpower) after reaching the minimum operating

VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5 V) voltage.

Document Number: 001-08350 Rev. *I

Page 6 of 18

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