CY7C1061DV18
16-Mbit (1M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
■ High Speed
❐ tAA = 15 ns
■ Low Active Power
❐ ICC = 150 mA at 67 MHz
■ Low complementary metal oxide semiconductor (CMOS)
Standby Power
❐ ISB2 = 25 mA
■ Operating voltages of 1.7 V to 2.2 V
■ 1.5 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-pin thin small outline package (TSOP)
Type II package and 48-ball Very Fine-Pitch Ball Grid Array
(VFBGA)
Functional Description
The CY7C1061DV18 is a high performance CMOS Static RAM
(SRAM) organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE1 LOW and CE2 HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7),
is written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
To read from the device, enable the chip by taking CE1 LOW and
CE2 HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O8 to I/O15. See the Truth Table
on page 12 for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV18 is available in a 54-pin TSOP II and 48-ball
VFBGA package with center power and ground (revolutionary)
pinout.
Logic Block Diagram
A0
A1
A2
AA34
AA56
AAA978
INPUT BUFFER
1M x 16
ARRAY
I/O0–I/O7
I/O8–I/O15
COLUMN
DECODER
BHE
WE
CE2
OE
CE1
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08350 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 22, 2014