CY7C1061DV18(2011) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1061DV18 Datasheet PDF : 14 Pages
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CY7C1061DV18
Figure 8. Write Cycle No. 3 (WE Controlled, OE Low)[21,22,23]
tWC
ADDRESS
CE
tSCE
tSA
WE
BHE, BLE
DATA I/O
tAW
tHA
tPWE
tBW
tHZWE
tSD
DATA IN VALID
tHD
tLZWE
Truth Table
CE1 CE2 OE WE BLE
HX
XX
X
X
L
XX
X
L
H
LH
L
L
H
LH
L
L H LH H
L HXL
L
L HXL
L
L
H
XL
H
L H HH X
BHE
I/O0–I/O7
X High Z
X High Z
L Data out
H Data out
L High -Z
L Data in
H Data in
L High Z
X High Z
I/O8–I/O15
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
Mode
Power-down
Power-down
Read all bits
Read lower bits only
Read upper bits only
Write all bits
Write lower bits only
Write upper bits only
Selected, outputs disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Notes
21. Data I/O is high impedance if OE or BHE and/or BLE = VIH.
22. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
23. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.
Document #: 001-08350 Rev. *G
Page 9 of 14
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