CY7C1061DV18(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C1061DV18
(Rev.:2011)

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

ADDRESS

CE

WE

BHE, BLE

DATA I/O

ADDRESS

BHE, BLE

WE

CE

DATA I/O

Figure 6. Write Cycle No. 1 (CE Controlled)[18,19,20]

tWC

CY7C1061DV18

tSA

tSCE

tAW

tHA

tPWE

tBW

tSD

tHD

DATA IN VALID

Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)

tWC

tSA

tAW

tBW

tHA

tPWE

tSCE

tSD

tHD

DATA IN VALID

Notes

18. Data I/O is high impedance if OE or BHE and/or BLE = VIH.

19. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

20. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH

Document #: 001-08350 Rev. *G

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