CY7C1061DV18-15ZSXI(2011) Просмотр технического описания (PDF) - Cypress Semiconductor

Номер в каталоге

Компоненты Описание

производитель

CY7C1061DV18-15ZSXI
(Rev.:2011)

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

Switching Waveforms

Figure 4. Read Cycle No. 1[14,15]

tRC

ADDRESS

DATA I/O

tAA

tOHA

PREVIOUS DATA VALID

CY7C1061DV18

DATA OUT VALID

ADDRESS

CE1

CE2

OE

BHE, BLE

DATA I/O

VCC

SUPPLY

CURRENT

Figure 5. Read Cycle No. 2 (OE Controlled)[16,17]

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

tHZOE

DATA OUT VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

ISB

Notes

14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

15. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH.

16. WE is HIGH for Read cycle.

17. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

Document #: 001-08350 Rev. *G

Page 7 of 14

Share Link: