LF3304 Просмотр технического описания (PDF) - LOGIC Devices

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LF3304

Dual Line Buffer/FIFO

LOGIC Devices 

DEVICES INCORPORATED

LF3304

Dual Line Buffer/FIFO

NOTES

1. Maximum Ratings indicate stress

specifications only. Functional oper-

ation of these products at values beyond

those indicated in the Operating Condi-

tions table is not implied. Exposure to

maximum rating conditions for ex-

tended periods may affect reliability.

2. The products described by this spec-

ification include internal circuitry de-

signedtoprotect the chipfromdamaging

substrate injection currents and accu-

mulations of static charge. Neverthe-

less, conventional precautions should

be observed during storage, handling,

and use of these circuits in order to avoid

exposure to excessive electrical stress

values.

3. This device provides hard clamping

of transient undershoot. Input levels

below ground will be clamped begin-

ning at –0.6 V. The device can withstand

indefinite operation with inputs or out-

puts in the range of –0.5 V to +5.5 V.

Device operation will not be adversely

affected, however, input current levels

will be well in excess of 100 mA.

input transition times less than 3 ns,

output reference levels of 1.5 V (except

tDIS test), and input levels of nominally

0 to 3.0 V. Output loading may be a

resistive divider which provides for

specified IOH and IOL at an output

voltage of VOH min and VOL max

respectively. Alternatively, a diode

bridge with upper and lower current

sources of IOH and IOL respectively,

and a balancing voltage of 1.5 V may be

used. Parasitic capacitance is 30 pF

minimum, and may be distributed.

This device has high-speed outputs ca-

pable of large instantaneous current

pulses and fast turn-on/turn-off times.

As a result, care must be exercised in the

testing of this device. The following

measures arerecommended:

a. A 0.1 µF ceramic capacitor should be

installed between VCC and Ground

leads as close to the Device Under Test

(DUT) as possible. Similar capacitors

should be installed between device VCC

and the tester common, and device

ground and tester common.

measured to the 1.5 V crossing point with

datasheet loads. For the tDIS test, the

transition is measured to the ±200mV

level from the measured steady-state

output voltage with ±10mA loads.

The balancing voltage, VTH, is set at

3.0 V for Z-to-0 and 0-to-Z tests, and

set at 0 V for Z-to-1 and 1-to-Z tests.

12. These parameters are only tested at

the high temperature extreme, which is

the worst case for leakage current.

FIGURE A. OUTPUT LOADING CIRCUIT

S1

DUT

CL

IOL

VTH

IOH

FIGURE B. THRESHOLD LEVELS

tENA

tDIS

OE

1.5 V

1.5 V

4. Actual test conditions may vary from b. Ground and VCC supply planes must

those designated but operation is guar- be brought directly to the DUT socket or

anteed as specified.

contactor fingers.

5. Supply current for a given applica-

tion can be accurately approximated

by:

NCV2 F

4

where

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with outputs changing every

cycle and no load, at a 40 MHz clock rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed but

not 100% tested.

9. AC specifications are tested with

c. Input voltages on a test fixture should

be adjusted to compensate for inductive

ground and VCC noise to maintain re-

quired DUT input levels relative to the

DUT ground pin.

10. Each parameter is shown as a mini-

mum or maximum value. Input require-

ments are specified from the point of view

of the external system driving the chip.

Setup time, for example, is specified as a

minimum since the external system must

supply at least that much time to meet the

worst-case requirements of all parts.

Responses from the internal circuitry are

specified from the point of view of the

device. Output delay, for example, is

specified as a maximum since worst-

case operation of any device always pro-

vides data within that time.

11. For the tENA test, the transition is

Z0

1.5 V

VOL* 0.2 V

3.0V Vth

0Z

Z1

1.5 V

VOH* 0.2 V

1Z

0V Vth

VOL* Measured VOL with IOH = –10mA and IOL = 10mA

VOH* Measured VOH with IOH = –10mA and IOL = 10mA

Video Imaging Products

11

08/16/2000–LDS.3304-F

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