ADRF6510 Просмотр технического описания (PDF) - Analog Devices

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производитель

ADRF6510

30 MHz Dual Programmable Filters and Variable Gain Amplifiers

Analog Devices 

ADRF6510

TIMING DIAGRAMS

tCLK

tPW

CLK

tLS

tLH

LE

tDS tDH

DATA

WRITE BIT

LSB

LSB + 1

MSB – 2

MSB – 1

MMSSBB- 2

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY

WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE CORNER FREQUENCY WORD BIT IS THEN

REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.

Figure 2. Write Mode Timing Diagram

tD

tCLK

tPW

CLK

tLH

tLS

LE

tDS tDH

DATA

READ BIT

DC

DC

DC

DC

DC

DC

DC

SDO

LSB

LSB + 1

MSB – 2

MSB – 1

MSB

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY WORD

REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE CORNER FREQUENCY WORD BIT IS THEN UPDATED AT

THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.

Figure 3. Read Mode Timing Diagram

Rev. 0 | Page 5 of 28

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