CY7C10612DV33(2009) Просмотр технического описания (PDF) - Cypress Semiconductor

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производитель

CY7C10612DV33
(Rev.:2009)

16-Mbit (1M x 16) Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14]

CY7C10612DV33

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

ADDRESS

CE

WE

BHE, BLE

DATA IO

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

IISSBB

Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16]

tWC

tSA

tSCE

tAW

tHA

tPWE

tBW

tSD

tHD

Notes

14. Address valid before or similar to CE transition LOW.

15. Data IO is high impedance if OE, BHE, and/or BLE = VIH.

16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

Document Number: 001-49315 Rev. *A

Page 7 of 10

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