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HI5662/6IN

Dual 8-Bit, 60MSPS A/D Converter with Internal Voltage Reference

Intersil 

HI5662

Electrical Specifications

ACVLC=C110,2pF=;DTVAC=C215,2oC=;+D5i.f0feVr,eDnVtiaClCA3n=al+o3g.0InVp;uVt;RUINnl=es2s.5O0tVh;efrSwi=se60SMpeScPifiSedat

50% Duty Cycle;

(Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Data Output Delay, tOD

Data Latency, tLAT

Power-Up Initialization

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

-

11.7

-

6

6

6

-

-

20

Sample Clock Pulse Width (Low)

(Note 2)

7.5

8.3

-

Sample Clock Pulse Width (High)

(Note 2)

7.5

8.3

-

Sample Clock Duty Cycle Variation

±5

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AVCC

Digital Supply Voltage, DVCC1 and DVCC2

Digital Output Supply Voltage, DVCC3

(Note 2)

(Note 2)

At 3.0V (Note 2)

At 5.0V (Note 2)

4.75

5.0

5.25

4.75

5.0

5.25

2.7

3.0

3.3

4.75

5.0

5.25

Supply Current, ICC

Power Dissipation

fS = 60MSPS

-

130

-

-

650

670

Offset Error Sensitivity, ∆VOS

AVCC or DVCC = 5V ±5%

Gain Error Sensitivity, ∆FSE

AVCC or DVCC = 5V ±5%

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

-

±0.125

-

-

±0.15

-

UNITS

ns

Cycles

Cycles

ns

ns

%

V

V

V

V

mA

mW

LSB

LSB

16

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