CAT24C256WI-GT3 Просмотр технического описания (PDF) - Unspecified

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CAT24C256WI-GT3

256 kb I2C CMOS Serial EEPROM

Unspecified 

CAT24C256

SCL

SDA

START

CONDITION

Figure 2. Start/Stop Timing

STOP

CONDITION

1

0

1

0 A2 A1 A0 R/W

DEVICE ADDRESS

Figure 3. Slave Address Bits

SCL FROM

MASTER

BUS RELEASE DELAY (TRANSMITTER)

1

8

BUS RELEASE DELAY (RECEIVER)

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACK DELAY (≤ tAA)

Figure 4. Acknowledge Timing

ACK SETUP (≥ tSU:DAT)

SCL

tSU:STA

SDA IN

tF

tHIGH

tLOW

tLOW

tHD:STA

tHD:DAT

tR

tSU:DAT

SDA OUT

tAA

tDH

Figure 5. Bus Timing

tSU:STO

tBUF

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5

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