MC100LVEL13 Просмотр технического описания (PDF) - ON Semiconductor

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производитель

MC100LVEL13

3.3VECL Dual 1:3 Fanout Buffer

ON Semiconductor 

MC100LVEL13

Q1a Q1a Q2a Q2a VCC Q2b Q2b Q1b Q1b VEE

20 19 18 17 16 15 14 13 12 11

Table 1. PIN DESCRIPTION

PIN

FUNCTION

Qna, Qna

Qnb, Qnb

CLKn, CLKn

VCC

VEE

ECL Differential Clock Outputs

ECL Differential Clock Outputs

ECL Differential Clock Inputs

Positive Supply

Negative Supply

1 2 3 4 5 6 7 8 9 10

Q0a Q0a VCC CLKa CLKa CLKb CLKb VCC Q0b Q0b

Warning: All VCC and VEE pins must be externally connected to

Power Supply to guarantee proper operation.

Figure 1. Logic Diagram and Pinout: 20−Lead SOIC

(Top View)

Table 2. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

PECL Mode Power Supply

VEE

NECL Mode Power Supply

VI

PECL Mode Input Voltage

NECL Mode Input Voltage

Iout

Output Current

VEE = 0 V

VCC = 0 V

VEE = 0 V

VCC = 0 V

Continuous

Surge

VI  VCC

VI  VEE

8 to 0

V

−8 to 0

V

6 to 0

V

−6 to 0

V

50

mA

100

mA

TA

Operating Temperature Range

Tstg

Storage Temperature Range

qJA

Thermal Resistance (Junction to Ambient) 0 lfpm

500 lfpm

20 SOIC

20 SOIC

−40 to +85

−65 to +150

90

60

°C

°C

°C/W

°C/W

qJC

Thermal Resistance (Junction to Case)

Standard Board

20 SOIC

Tsol

Wave Solder

Pb <2 to 3 sec @ 248°C

Pb−Free <2 to 3 sec @ 260°C

30 to 35

265

265

°C/W

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may

affect device reliability.

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