ADSP-21160NKB-95 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21160NKB-95

DSP Microcomputer

Analog Devices 

PRELIMINARY TECHNICAL DATA

April 2002

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

ADSP-21160#6

ADSP-21160#5

ADSP-21160#4

ADSP-21160#3

CLKIN ADDR31–0

RESET DATA63–0

RPBA

3

ID2–0

CONTROL

011

PA

BR1–2, BR4–6 5

BR3

ADSP-21160#2

CLKIN ADDR31–0

RESET DATA63–0

RPBA

3

ID2–0

010

CONTROL

PA

BR1, BR3–6 5

BR2

ADSP-21160#1

CLKIN

ADDR31–0

RESET

DATA63–0

RPBA

RDx

WRx

3

ID2–0

ACK

MS3–0

001

BMS

PAGE

SBTS

RESET

CLOCK

CLKOUT

CS

HBR

HBG

REDY

PA

BR2–6 5

BR1

ADDR

DATA

OE

WE

ACK

CS

CS

ADDR

DATA

GLOBALMEMORY

AND

PERIPHERAL(OPTIONAL)

BOOTEPROM(OPTIONAL)

ADDR

DATA

HOSTPROCESSOR

INTERFACE(OPTIONAL)

Figure 4. Shared Memory Multiprocessing System

cally transferred to and from on-chip memory via a

dedicated DMA. Each of the serial ports offers a TDM

multichannel mode. The serial ports can operate with lit-

tle-endian or big-endian transmission formats, with word

lengths selectable from 3 bits to 32 bits. They offer selectable

synchronization and transmit modes as well as optional

µ-law or A-law companding. Serial port clocks and frame

syncs can be internally or externally generated.

Host Processor Interface

The ADSP-21160N host interface allows easy connection

to standard microprocessor buses, both 16-bit and 32-bit,

with little additional hardware required. The host interface

is accessed through the ADSP-21160N’s external port and

is memory-mapped into the unified address space. Four

channels of DMA are available for the host interface; code

and data transfers are accomplished with low software

overhead. The host processor communicates with the

ADSP-21160M’s external bus with host bus request

(HBR), host but grant (HBG), ready (REDY), acknowledge

(ACK), and chip select (CS) signals. The host can directly

read and write the internal memory of the ADSP-21160N,

and can access the DMA channel setup and mailbox regis-

ters. Vector interrupt support provides efficient execution

of host commands.

Program Booting

The internal memory of the ADSP-21160N can be booted

at system power-up from an 8-bit EPROM, a host proces-

sor, or through one of the link ports. Selection of the boot

source is controlled by the BMS (Boot Memory Select),

EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)

pins. 32-bit and 16-bit host processors can be used

for booting.

Phased Locked Loop

The ADSP-21160N uses an on-chip PLL to generate the

internal clock for the core. Ratios of 2:1, 3:1, and 4:1

between the core and CLKIN are supported. The

CLK_CFG pins are used to select the ratio. The CLKIN

rate is the rate at which the synchronous external

port operates.

Power Supplies

The ADSP-21160N has separate power supply connections

for the internal (VDDINT), external (VDDEXT), and analog

(AVDD/AGND) power supplies. The internal and analog

supplies must meet the 1.9 V requirement. The external

supply must meet the 3.3 V requirement. All external supply

pins must be connected to the same supply.

The PLL Filter Figure 5 on page 7 must be added for each

ADSP-21160N in the system. VDDint is the digital core

supply. It is recommended that the capacitors be connected

directly to AGND using short thick trace. It is recom-

mended that the capacitors be placed as close to AVDD and

AGND as possible. The connection from AGND to the

(digital) ground plane should be made after the capacitors.

The use of a thick trace for AGND is reasonable only

because the PLL is a relatively low power circuit - it does

not apply to any other ADSP-21160N GND connection.

REV. PrB This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

6

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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