MAS3528E Просмотр технического описания (PDF) - Micronas

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MAS3528E

Dolby Digital and MPEG-1 Layer-2 Audio Decoder

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ADVANCE INFORMATION

MAS 3528E

2.4. Internal Program ROM and Firmware

The firmware implemented in the program ROM of the

MAS 3528E provides Dolby Digital decoding including

the required downmixing, output configurations and

delay lines (part of an Implementation of Dolby Digital),

MPEG-1 Layer-2 audio data decompression, handling

of PCM-encoded audio, and loop-through of DTS-for-

mats received via the S/PDIF-input.

For PCM and MPEG-signals, a deemphasis can be

applied to achieve a flat frequency response as

required by Dolby Pro Logic decoders.

On power-on, the DSP starts the firmware in an auto-

matic standard detection mode with the S/PDIF-input

selected. Therefore, only minimal controlling is neces-

sary. In addition, the I2C-interface provides a set of I2C

instructions that give access to internal DSP-registers

and memory areas.

2.5. RAM and Registers

The DSP-core has access to two RAM-banks denoted

D0 and D1. All RAM-addresses can be accessed in a

20-bit or a 16-bit mode via I2C-bus. For more details,

please refer to Section 3.4. on page 18.

For fast access of internal DSP-states, the processor

core has an address space of 256 data registers (see

Section 3.5. on page 23) which can be accessed via

I2C-bus.

2.5.1. Program Download Feature

The overall function of the MAS 3528E can be altered

by downloading up to 4 kWords of program code into

the internal RAM and executing this code instead of

the ROM code. While using such alternate program

code, no Dolby Digital or MPEG-decoding is possible.

All information concerning the download feature will be

distributed together with the download code.

2.6. Clock Management

The MAS 3528E is driven by a single clock at a fre-

quency of 18.432 MHz. The clock may either be pro-

vided from an external source to pin XTI or generated

with a crystal. At pin XTO, the clock signal is available

for other applications.

The internal reference clock and processor clock are

derived from the 18.432 MHz and synchronized to the

audio sample frequency of the decompressed bit

stream by a PLL. In case of Dolby Digital decoding, the

clock frequency may be selected between a high and a

low value by bit[16] in configuration memory cell

UIC_Out_Clk_Scale (D0:13DF) – (see Table 3–7 on

page 32).

The resulting processor clocks are given in Table 2–1.

At pin CLKO, a clock output can be provided e.g. for

additional D/A-converters. The output frequency at

CLKO is the reference clock divided by a factor as

selected by bits[18:17] in D0:13DF. By default, CLKO is

disabled..

Table 2–1: Processor clock frequencies in

dependence of bit[16] of

UIC_Out_Clk_Scale (D0:13DF).

Format

fs/kHz

Dolby

48

Digital

44.1

32

MPEG,

48

PCM

44.1

32

Processor Clock/MHz

bit[16] = 0 bit[16] = 1

61.44

73.728

56.448

67.7376

40.96

49.152

36.864

33.8688

24.576

Table 2–2: Reference clock frequencies in

dependence of bit[16] of

UIC_Out_Clk_Scale (D0:13DF).

Format

fs/kHz

Dolby

48

Digital

44.1

32

MPEG,

48

PCM

44.1

32

Reference Clock/MHz

bit[16] = 0 bit[16] = 1

61.44

73.728

56.448

67.7376

40.96

49.152

73.728

67.7376

49.152

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