PEB20534 Просмотр технического описания (PDF) - Infineon Technologies

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PEB20534

DMA Supported Serial Communication Controller with 4 Channels

Infineon Technologies 

DMA Supported Serial Communication Controller with

4 Channels

DSCC4

PEB 20534

PEF 20534

Version 2.1

1.1

Features

Serial Communication Controllers (SCCs)

• Four independent channels

• Full duplex data rates on each channel of up to

10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async

• Full duplex data rate of up to 52 Mbit/s on any two

channels in high speed mode (HDLC: Address

Mode 0 and extended transparent protocol mode);

up to 45 Mbit/s on any two channels in high speed

mode (HDLC: PPP modes). The aggregate

bandwith for all channels is limited to 108 Mbit/s per

direction.

• 17 DWORDs deep receive FIFO per SCC

(+ 128 DWORDs central receive FIFO).

• 8 DWORDs deep transmit FIFO per SCC

(+ 128 DWORDs central transmit FIFO).

P-FQFP-208-7

CMOS

Serial Interface

• On-chip clock generation or external clock sources

• On-chip DPLLs for clock recovery

• Baud rate generator

• Clock gating signals

• Clock gapping capability

• Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1)

• NRZ, NRZI, FM and Manchester data encoding

• Optional data flow control using modem control lines (RTS, CTS, CD)

• Support of bus configuration by collision detection and resolution

Type

PEB 20534 H-10

PEF 20534 H-10

PEB 20534 H-52

Data Sheet

Package

P-FQFP-208-7

P-FQFP-208-7

P-FQFP-208-7

19

2000-05-30

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