PEB20534 Просмотр технического описания (PDF) - Infineon Technologies

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Компоненты Описание

производитель

PEB20534

DMA Supported Serial Communication Controller with 4 Channels

Infineon Technologies 

PEB 20534

PEF 20534

List of Figures

Page

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Interrupt Vector Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 399

Power-up and Power-down scenarios . . . . . . . . . . . . . . . . . . . . . . . . 406

Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 411

PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . 411

PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . 412

PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Master Single READ Transaction followed by a Master Single

WRITE Transaction in De-multiplexed Bus Configuration . . . . . . . . . 418

Master Burst WRITE/READ Access in De-multiplexed

Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Synchronous LBI Read Cycle Timing Multiplexed Bus . . . . . . . . . . . 420

Synchronous LBI Write Cycle Timing Multiplexed Bus . . . . . . . . . . . 420

Synchronous LBI Read Cycle Timing De-multiplexed Bus . . . . . . . . 422

Synchronous LBI Write Cycle Timing De-multiplexed Bus . . . . . . . . 422

LRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

LBI Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

High Speed Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

High Speed Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

SSC Interface Timing (Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

Data Sheet

12

2000-05-30

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