XRT91L80 Просмотр технического описания (PDF) - Exar Corporation

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производитель

XRT91L80

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

Exar Corporation 

xr

REV. P1.1.0

RECEIVER SECTION

NAME

LEVEL

RXDO0P

RXDO0N

RXDO1P

RXDO1N

RXDO2P

RXDO2N

RXDO3P

RXDO3N

LVDS

RXPCLKOP

RXPCLKON

LVDS

DISRD

LVTTL

LVCMOS

RXIP

RXIN

CMLDIFF

XRES1P

-

XRES1N

RXCLKO16P

RXCLKO16N

LVDS

LOCKDET_CDR LVCMOS

SDEXT

LVTTL,

LVCMOS

PRELIMINARY

XRT91L80

2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

TYPE

O

O

I

I

I

O

O

I

PIN

DESCRIPTION

E13 Receive Parallel Data Output

F13 622Mbps 4-bit parallel receive data output is updated simulta-

C14 neously on the rising edge of the RXPCLKOP/N output. The 4-

D14 bit parallel interface is de-multiplexed from the receive serial

C13 data input MSB first (RXDO3P/N).

D13 NOTE: The XRT91L80 can output 666.51 Mbps 4-bit parallel

receive data output for Forward Error Correction (FEC)

A14

Applications.

B14

E14 Receive Parallel Clock Output

F14 622.08 MHz parallel clock output used to update the 4-bit paral-

lel receive data output RXDO[3:0]P/N at the rising edge of this

clock..

NOTE: The XRT91L80 can output a 666.51 MHz receive clock

output for Forward Error Correction (FEC).

C12 Parallel Receive Data Output Disable

This pin is used to disable the RXDO[3:0]P/N parallel receive

data output bus asynchronously.

"Low" = Normal Mode

"High" = Forces RXDO[3:0]P/N to a logic state "0"

This pin is provided with an internal pull-down.

C1 Receive Serial Data Input

D1 The receive serial data stream of 2.488 Gbps is applied to

these input pins. In Forward Error Correction, the receive

serial data stream is 2.666 Gbps.

G1 External LVDS Biasing Resistors

F1 A 402Ω resistor with +/-1% tolerance should be placed across

these 2 pins for proper biasing.

A6 Auxiliary Clock Output (155.52/166.63 MHz)

A7 155.52/166.63 MHz auxiliary clock derived from divide-by-16

CDR recovered clock.

C7 CDR Lock Detect

This pin is used to monitor the lock condition of the clock and

data recovery unit.

"Low" = CDR Out of Lock

"High" = CDR Locked

B5 Signal Detect Input from Optical Module

Hardware Mode When inactive, it will immediately declare a

Loss of Signal Detect (LOSD) condition and assert LOSDET

output pin and control the activity of the RXDO[3:0]P/N parallel

data output based on LOSDMUTE pin setting.

Host Mode In addition to asserting LOSDET output pin, it will

update the LOSD condition on the registers and control the

activity of the RXDO[3:0]P/N parallel data output based on

LOSDMUTE register bit setting.

"Active" = Normal Operation

"Inactive" = LOSD Condition (SDEXT detects signal absence)

This pin is provided with an internal pull-down.

9

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