XRT91L33 Просмотр технического описания (PDF) - Exar Corporation
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XRT91L33 Datasheet PDF : 16 Pages
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XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
1.0 PIN DESCRIPTIONS
TABLE 2: PIN DESCRIPTION TABLE
REV. V1.0.0
NAME
VDDA
RXDIP
RXDIN
VSSA
LEVEL
PWR
LVDS/PECL
TYPE
PWR
I
LVDS/PECL
I
PWR
PWR
PIN
DESCRIPTION
1
3.3V Power supply
2
Positive side of receive data input. The high-speed output clock
(RXCLKOP/N) is recovered from this high-speed differential
inupt data.
3
Negative side of receive data input. The high-speed output
clock (RXCLKOP/N) is recovered from this high-speed differen-
tial input data.
4
Ground pin
LOCK
LVPECL
O
STS12_MODE
LVTTL
I
REFCK
LVTTL
I
LCKTOREFN
LVTTL
I
VSS
VDD
RXCLKON
RXCLKOP
RXDON
RXDOP
PWR
PWR
LVDS/
LVPECL
LVDS/
LVPECL
LVDS/
LVPECL
LVDS/
LVPECL
PWR
PWR
O
O
O
O
5
Active HIGH to indicate that the PLL is locked to serial data
input and valid clock and data are present at the serial outputs
(RXDOP/N and RXCLKOP/N). The LOCK will go inactive under
the following conditions:
• If SIGD is set LOW
• If LCKTOREFN is set LOW
• If the VCO has drifted away from the local reference
clock, REFCK, by more than +/- 500 ppm
6
STS-12 or STS-3 mode selection. Set HIGH to select the
STS-12 operation. Set LOW for STS-3 operation
7
Local 19.44 MHz reference clock input for the CDR. REFCK is
used for the PLL phase adjustment during power up. It also
serves as a stable clock source in the absence of serial input
data.
8
Lock to REFCK input. When set LOW, this pin causes the out-
put clock, RXCLKOP/N to be held within +/- 500ppm of the
input reference clock REFCL and forces the RXDOP/N to a low
state.
9
Ground pin
10 3.3V power supply
11 High-speed clock output, negative. This clock is recovered
from the receive data input (RXDIP/N) and supports either
LVDS or LVPECL termination
12 High-speed clock output, positive This clock is recovered from
the receive data input (RXDIP/N) and supports either LVDS or
LVPECL. termination
13 High-speed output, negative This is the retimed version of the
recovered data stream from RXDIP/N and can be in either LVDS
or LVPECL termination
14 High-speed output, positive. This is the retimed version of the
recovered data stream from RXDIP/N and can be in either
LVDS or LVPECL termination
4
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