XRT91L31IQ(2006) Просмотр технического описания (PDF) - Exar Corporation
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XRT91L31IQ Datasheet PDF : 41 Pages
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XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN DESCRIPTIONS
xr
REV. 1.0.2
HARDWARE CONTROL
NAME
RESET
LEVEL
LVTTL,
LVCMOS
TYPE
I
STS12/STS3
LVTTL,
I
LVCMOS
CMUFREQSEL
LVTTL,
I
LVCMOS
CDR_BW/VDD
LVTTL,
I
LVCMOS
PIN
DESCRIPTION
1
Master Reset Input
Active "High." When this pin is pulled "High" , the internal state
machines are set to their default state.
"Low" = Normal Operation
"High" = Master Hardware Reset
59 Data Rate Selection
Selects SONET/SDH transmission and reception speed rate
"Low" = STS-3/STM-1 155.52 Mbps
"High" = STS-12/STM-4 622.08 Mbps
3
Clock Multiplier Unit Reference Frequency Select
This pin is used to select the frequency of the REFCLKP/N or
TTLREFCLK input to the CMU.
"Low" = 77.76 MHz reference clock
"High" = 19.44 MHz reference clock
CMU-
FREQSEL
0
STS12/
STS3
0
REFCLKP/N OR
TTLREFCLK
REFERENCE
FREQUENCY
77.76 MHz
0
1
77.76 MHz
1
0
19.44 MHz
1
1
19.44 MHz
DATA RATE
STS-3/STM-1
155.52 Mbps
STS-12/STM-4
622.08 Mbps
STS-3/STM-1
155.52 Mbps
STS-12/STM-4
622.08 Mbps
NOTE: REFCLKP/N or TTLREFCLK input should be generated
from an LVPECL/LVTTL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the
transmitted data rate frequency to have the necessary
accuracy required for SONET systems..
15 CDR Bandwidth Select
This pin is used to select the CDR Bandwidth
"Low" = Narrow BW, (SONET Jitter Transfer and Jitter Toler-
ance)
"High" (VDD) = Wide BW (Better jitter tolerance)
4
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