XRT72L52 Просмотр технического описания (PDF) - Exar Corporation
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XRT72L52 Datasheet PDF : 480 Pages
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TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
TABLE OF CONTENTS
XRT72L52
REV. 1.0.1
GENERAL DESCRIPTION................................................................................................. 1
FEATURES................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT72L52 ....................................................................................................................... 1
Figure 2. Pin Out of the XRT72L52 .................................................................................................................................. 2
ORDERING INFORMATION .............................................................................................. 2
TABLE OF CONTENTS .................................................................................................................................. I
PIN DESCRIPTIONS .......................................................................................................... 3
ELECTRICAL CHARACTERISTICS................................................................................ 22
ABSOLUTE MAXIMUMS............................................................................................................................... 22
DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 22
AC ELECTRICAL CHARACTERISTICS ........................................................................................................... 22
AC ELECTRICAL CHARACTERISTICS (CONT.) .............................................................................................. 24
1.0 Timing Diagrams ................................................................................................................................ 28
Figure 3. Timing Diagram for Transmit Payload Input Interface, when the XRT72L52 is operating in both the DS3 and Loop-
Timing Modes .................................................................................................................................................. 28
Figure 4. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L52 is operating in both the DS3 and
Local-Timing Modes ........................................................................................................................................ 28
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 is operating in both the DS3/
Nibble and Looped-Timing Modes................................................................................................................... 29
Figure 6. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L52 is operating in the DS3/Nibble
and Local-Timing Modes ................................................................................................................................. 29
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) ..................................... 30
Figure 8. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) ..................................... 30
Figure 9. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the rising edge of TxLineClk ................ 31
Figure 10. Transmit LIU Interface Timing - TxPOS and TxNEG are updated on the falling edge of TxLineClk ............. 31
Figure 11. Receive LIU Interface timing - RxPOS and RxNEG are sampled on rising edge of RxLineClk..................... 32
Figure 12. Receive LIU Interface timing - RxPOS and RxNEG are sampled on falling edge of RxLineClk ................... 32
Figure 13. Receive Payload Data Output Interface Timing............................................................................................. 33
Figure 14. Receive Payload Data Output Interface Timing (Nibble Mode Operation) .................................................... 33
Figure 15. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ........................................... 34
Figure 16. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ..................................... 34
Figure 17. Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation ........................................... 35
Figure 18. Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation............................................ 35
Figure 19. Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................... 36
Figure 20. Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................... 36
Figure 21. Microprocessor Interface Timing - Reset Pulse Width................................................................................... 36
2.0 The Microprocessor Interface Block ................................................................................................ 37
Figure 22. Block Diagram of the Microprocessor Interface Block ................................................................................... 37
2.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNASL .......................................................................................... 37
TABLE 1: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND
MOTOROLA MODES ........................................................................................................................................... 38
TABLE 2: DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE INTEL MODE ................................. 38
TABLE 3: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS - OPERATING IN THE MOTOROLA MODE.................. 39
2.2 INTERFACING THE XRT72L52 DS3/E3 FRAMER TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK
39
2.2.1 Interfacing the XRT72L52 DS3/E3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
39
2.2.2 Data Access Modes ............................................................................................................................... 40
Figure 23. Microprocessor Interface Timing - Intel-type Programmed I/O Read Operation ........................................... 41
Figure 24. Microprocessor Interface Timing - Intel-type Programmed I/O Write Operation............................................ 42
Figure 25. Microprocessor Interface Timing - Motorola-type Programmed I/O Read Operation .................................... 43
Figure 26. Microprocessor Interface Timing - Motorola-type Programmed I/O Write Operation .................................... 44
2.3 ON-CHIP REGISTER ORGANIZATION ................................................................................................................... 44
2.3.1 Framer Register Addressing .................................................................................................................. 44
TABLE 4: REGISTER ADDRESSING OF THE FRAMER PROGRAMMER REGISTERS.................................................................... 44
2.3.2 Framer Register Description .................................................................................................................. 48
PART NUMBER REGISTER (ADDRESS = 0X02) ............................................................................................ 51
VERSION NUMBER REGISTER (ADDRESS = 0X03)....................................................................................... 52
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