XRT72L52(2001) Просмотр технического описания (PDF) - Exar Corporation

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XRT72L52
(Rev.:2001)

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

XRT72L52

TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. P1.1.3

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PRELIMINARY

face block of the XRT72L52 for Mode 2 (Serial/Local-Timed/Frame-Slave) Operation ...................... 151

Figure 47. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment

(Mode 2 Operation) ............................................................................................................................. 152

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 152

Figure 48. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-

face block of the XRT72L52 for Mode 3 (Serial/Local-Timed/Frame-Master) Operation .................... 153

Figure 49. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment

(DS3 Mode 3 Operation) ..................................................................................................................... 154

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 155

Figure 50. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-

face block of the XRT72L52 for Mode 4 (Nibble-Parallel/Loop-Timed) Operation .............................. 156

Figure 51. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment

(Mode 4 Operation) ............................................................................................................................. 157

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 157

Figure 52. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-

face block of the XRT72L52 for Mode 5 (Nibble-Parallel/Local-Timed/Frame-Slave) Operation ........ 159

Figure 53. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment

(DS3 Mode 5 Operation) ..................................................................................................................... 160

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 160

Figure 54. Illustration of the Terminal Equipment being interfaced to the Transmit Payload Data Input Inter-

face block of the XRT72L52 for Mode 6 (Nibble-Parallel/Local-Timed/Frame-Master) Operation ...... 161

Figure 55. Behavior of the Terminal Interface signals between the XRT72L52 and the Terminal Equipment

(DS3 Mode 6 Operation) ..................................................................................................................... 162

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ..................................................................... 163

4.2.2 The Transmit Overhead Data Input Interface ........................................................................................ 163

Figure 56. Simple Illustration of the Transmit Overhead Data Input Interface block .......................... 163

TABLE 20: A LISTING OF THE OVERHEAD BITS WITHIN THE DS3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN

THE XRT72L52 IC ................................................................................................................................ 164

TABLE 21: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ...................... 165

Figure 57. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input In-

terface (Method 1) ............................................................................................................................... 166

TABLE 22: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXO-

HFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING PROCESSED ............... 167

Figure 58. Illustration of the signal that must occur between the Terminal Equipment and the XRT72L52,

in order to configure the XRT72L52 to transmit a Yellow Alarm to the remote terminal equipment .... 169

TABLE 23: DESCRIPTION OF METHOD 2 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ...................... 170

Figure 59. Illustration of the Terminal Equipment being interfaced to the Transmit Overhead Data Input In-

terface (Method 2) ............................................................................................................................... 171

TABLE 24: THE RELATIONSHIP BETWEEN THE NUMBER OF TXOHENABLE PULSES (SINCE THE LAST OCCURRENCE

OF THE TXOHFRAME PULSE) TO THE DS3 OVERHEAD BIT, THAT IS BEING PROCESSED BY THE XRT72L52 172

Figure 60. Behavior of Transmit Overhead Data Input Interface signals between the XRT72L52 and the

Terminal Equipment (for Method 2) ..................................................................................................... 174

4.2.3 The Transmit DS3 HDLC Controller ...................................................................................................... 174

TX DS3 FEAC REGISTER (ADDRESS = 0X32) ........................................................................................ 175

TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31) ............................... 175

TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31) ............................... 175

Figure 61. A Flow Chart depicting how to transmit a FEAC Message via the FEAC Transmitter ...... 176

Figure 62. LAPD Message Frame Format .......................................................................................... 177

TABLE 25: THE LAPD MESSAGE TYPE AND THE CORRESPONDING VALUE OF THE FIRST BYTE, WITHIN THE INFOR-

MATION PAYLOAD .................................................................................................................................. 177

TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................... 178

TABLE 26: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE .................. 178

TRANSMIT DS3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) ................................................... 178

TABLE 27: RELATIONSHIP BETWEEN TXLAPD MSG LENGTH AND THE LAPD MESSAGE SIZE .................. 178

TRANSMIT DS3 LAPD STATUS/INTERRUPT REGISTER (ADDRESS = 0X34) ............................................... 179

VI

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