XRT72L50 Просмотр технического описания (PDF) - Exar Corporation

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XRT72L50

SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

Exar Corporation 

XRT72L50

SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. 1.2.1

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2.3.8.18 One-Second Frame Parity Error Accumulator Register - LSB .................................................. 112

2.3.8.19 One-Second Frame CP-Bit Error Accumulator Register - MSB ................................................ 113

2.3.8.20 One-Second Frame CP-Bit Error Accumulator Register - LSB ................................................. 113

2.3.8.21 Line Interface Drive Register ..................................................................................................... 113

2.3.8.22 Line Interface Scan Register ..................................................................................................... 116

2.3.8.23 HDLC Control Register ............................................................................................................. 117

2.4 THE LOSS OF CLOCK ENABLE FEATURE ............................................................................................................. 117

2.5 USING THE PMON HOLDING REGISTER .............................................................................................................. 118

2.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ................................. 118

TABLE 5: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL OF THE XRT72L50

FRAMER ........................................................................................................................................................ 119

TABLE 6: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICATIONS) ..................... 119

TABLE 7: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832 APPLICATIONS) .. 120

TABLE 8: A LISTING OF THE XRT72L50 FRAMER INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751 APPLICATIONS) ... 120

2.6.1 Automatic Reset of Interrupt Enable Bits ............................................................................................... 122

TABLE 9: INTERRUPT SERVICE ROUTINE GUIDE (FOR DS3 APPLICATIONS) ...................................................................... 122

TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS) ................................................. 122

TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS) ................................................. 122

2.6.2 One-Second Interrupts .......................................................................................................................... 123

3.0 The Line Interface and scan section ................................................................................................ 124

3.1 BIT-FIELDS WITHIN THE LINE INTERFACE DRIVE REGISTER .................................................................................. 124

Figure 27. XRT72L50 DS3/E3 Framer Interfaced to the XRT73L0x DS3/E3/STS-1 LIU ............................................ 124

TABLE 12: THE RELATIONSHIP BETWEEN THE STATES OF RLOOP, LLOOP AND THE RESULTING LOOP-BACK MODE WITH THE

XRT73L0X .................................................................................................................................................... 126

3.2 BIT-FIELDS WITHIN THE LINE INTERFACE SCAN REGISTER ................................................................................... 127

4.0 DS3 Operation of the XRT72L50 ....................................................................................................... 129

4.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS ............................................................... 129

Figure 28. DS3 Frame Format for C-bit Parity ............................................................................................................ 129

Figure 29. DS3 Frame Format for M13 ....................................................................................................................... 130

TABLE 13: BIT 2 SETTING WITHIN THE FRAMER OPERATING MODE REGISTER AND THE RESULTING DS3 FRAMING FORMAT 130

4.1.1 Frame Synchronization Bits (Applies to both M13 and C-bit Parity Framing Formats) ......................... 131

4.1.2 Performance Monitoring/Error Detection Bits (Parity) ........................................................................... 131

TABLE 14: C-BIT FUNCTIONS FOR THE C-BIT PARITY DS3 FRAME FORMAT ...................................................................... 131

4.1.3 Alarm and Signaling-Related Overhead Bits ......................................................................................... 132

4.1.4 The Data Link Related Overhead Bits ................................................................................................... 133

4.2 THE TRANSMIT SECTION OF THE XRT72L50 (DS3 MODE OPERATION) ............................................................... 133

Figure 30. The XRT72L50 Transmit Section configured to operate in the DS3 Mode ................................................ 134

4.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 135

Figure 31. The Transmit Payload Data Input Interface Block ...................................................................................... 135

TABLE 15: DESCRIPTIONS FOR THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ................... 135

4.2.1.1 Mode 1 - Serial/Loop-Timing Mode Behavior of the XRT72L50 .................................................. 136

Figure 32. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 1(Serial/

Loop-Timed) Operation ................................................................................................................................ 137

Figure 33. Behavior of the Terminal Interface signals between the Transmit Payload Data Input Interface block of the

XRT72L50 and the Terminal Equipment (Mode 1 Operation) ...................................................................... 138

4.2.1.2 Mode 2 - The Serial/Local-Timed/Frame-Slave Mode Behavior of the XRT72L50 ..................... 139

Figure 34. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 2 (Serial/

Local-Timed/Frame-Slave) Operation .......................................................................................................... 140

4.2.1.3 Mode 3 - The Serial/Local-Timed/Frame-Master Mode Behavior of the XRT72L50 ................... 141

Figure 35. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 2

Operation) .................................................................................................................................................... 141

Figure 36. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 3 (Serial/

Local-Timed/Frame-Master) Operation ........................................................................................................ 142

4.2.1.4 Mode 4 - The Nibble-Parallel/Loop-Timed Mode Behavior of the XRT72L50 ............................. 143

Figure 37. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (DS3 Mode 3

Operation) .................................................................................................................................................... 143

Figure 38. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 4 (Nibble-

Parallel/Loop-Timed) Operation ................................................................................................................... 144

Figure 39. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 4

Operation) .................................................................................................................................................... 145

4.2.1.5 Mode 5 - The Nibble-Parallel/Local-Timed/Frame-Slave Interface Mode Behavior of the XRT72L50

146

IV

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