XE1203 Просмотр технического описания (PDF) - Unspecified

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производитель

XE1203

433MHz / 868MHz / 915MHz Low-power, integrated UHF transceiver

Unspecified 

Data Sheet

XE1203

dclk

@1154 Hz

information data

from a microcontroller

bit0

bit rate = 1154 bps

bit1

bit2

bit3

bit4

bit5

bit6

Spread data

@12.7 Kchps

spread

bit0

spread spread

bit1

bit2

spread

bit3

spread

bit4

spread

bit5

Figure 4 Data exchange during reception mode when barker scheme is used.

4.1.7 Pattern recognition block

This feature can be activated by setting RTParam_Pattern to high while in receiver mode. The incoming NRZ bit

stream is compared with a pattern stored in PATParam_Pattern registers. The PATTERN output is driven by the

output of this comparator and is synchronized by DCLK. It is set to high when a matching condition is detected,

otherwise set to low. PATTERN output is updated at the rising edge of DCLK. The number of bits used for

comparison is defined in ADParam_Psize register and the number of tolerated errors for the pattern recognition is

defined in ADParam_Ptol register. The next figure shows the pattern matching operation.

DATA

(NRZ)

Bit N-x =

Pattern[x]

DCLK

Bit N-1 =

Pattern[1]

Bit N =

Pattern[0]

PATTERN

Figure 5. Pattern matching operation.

12

D0308-214

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