AD9501JN(RevB) Просмотр технического описания (PDF) - Analog Devices
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AD9501JN Datasheet PDF : 12 Pages
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AD9501
THEORY OF OPERATION
Figure 2 illustrates in detail how the delay is determined.
The AD9501 is a digitally programmable delay device. Its func-
tion is to provide a precise incremental delay between input and
Minimum delay (tPD) is the sum of trigger circuit delay, ramp
generator delay, and comparator delay.
output, proportional to an 8-bit digital word applied to its delay
control port. Incremental delay resolution is 10 ps at the mini-
mum full-scale range of 2.5 ns. Digital delay data inputs, latch,
trigger, and reset are all TTL/CMOS-compatible. Output is
TTL-compatible.
The trigger circuit delay and comparator delay are fixed;
ramp generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Refer to the AD9501 Functional Block Diagram.
Maximum delay is the sum of minimum delay (tPD) and full-scale
program delay (tDFS).
Inside the unit, there are three main subcircuits: a linear ramp Ramp generator delay is the time required for the ramp to slew
generator, an 8-bit digital-to-analog converter (DAC), and a
from its reset voltage to the most positive DAC reference volt-
OBSOLETE voltage comparator. The rising edge of the input (TRIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
The voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage crosses
the threshold set by the DAC output voltage. The DAC thresh-
old voltage is programmed by the user with digital inputs.
age (00H). The difference in these two voltages is nominally
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
TRIGGER
DELAYED OUTPUT
COMPARATOR
DELAY
RESET
DAC REFERENCE
TRIGGER RAMP
CIRCUIT GEN.
DELAY DELAY
PROGRAMMED
DELAY
RESET PROP
DELAY (tRD)
LINEAR RAMP
SETTLING TIME
(tLRS)
(00H)
(tD)
PROGRAMMED
DAC THRESHOLD
(XXH)
RAMP GEN.
DELAY
DAC REFERENCE
(FFH)
PROGRAMMED
DELAY (tD)
FULL-SCALE
DELAY
RANGE
FULL–SCALE DELAY RANGE
(tD)
TRIGGER
INPUT
TRIGGER
GENERATOR
RAMP
GENERATOR
DAC
COMPARATOR
MINIMUM PROPAGATION DELAY = (tPD) = TRIGGER CIRCUIT DELAY + RAMP GENERATOR DELAY + COMPARATOR DELAY
MAXIMUM PROPAGATION DELAY = MINIMUM PROPAGATION DELAY (tPD) + FULL–SCALE RANGE (tDFS)
PROGRAMMED DELAY (tD) =
TOTAL DELAY = (tPD) + (tD)
DIGITAL VALUE
256
AD9501 TESTED WITH CEXT = 0 pF; RSET = 3.09 k⍀ (100 ns PROGRAMMED DELAY)
Figure 2. Internal Timing
REV. B
–5–
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