AD9501JN(RevB) Просмотр технического описания (PDF) - Analog Devices

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AD9501JN
(Rev.:RevB)

Digitally Programmable Delay Generator

Analog Devices 

AD9501

Analog Settling Time Measurement

Layout Considerations

The circuit shown in Figure 11 functions in a manner similar to Although the inputs and output of the AD9501 are digital, the

the digital delay detector; for this application, the clock must

delay is determined by analog circuits. This makes it critical to

be repetitive also. As in the delay detector, AD9501 #1 is used use high speed analog circuit layout techniques to achieve rated

to cancel the propagation delay of AD9501 #2, propagation performance.

delay of the comparators, and stray delays. To accomplish this,

use the calibration procedure described earlier for the digital

delay generator.

The ground plane should be on the component side of the

board and extend under the AD9501 to shield it from digital

switching signals. Most socket assemblies add significant

The difference between the two circuits is in the detection method. inter-lead capacitance and should be avoided whenever possible.

The register of the digital delay is replaced by a window com- If sockets must be used, individual pin sockets, such as TYCO

parator for the analog settling measurement.

part numbers 5-330808-3 (closed end) or 5-330808-6 (open end),

Threshold voltages V1 and V2 are set for the desired tolerance

should be used.

around the final value of the DUT output signal. As shown in Power supply decoupling is also critical for high speed design; a

OBSOLETE the lower portion of the diagram, the output of the detector is

HIGH when the analog output signal of the converter is within

the limits set by V1 and V2.

Therefore, the settling time can be measured by starting the delay

of AD9501 #2 at its maximum setting and decrementing it until

the window comparator goes low. The difference between the

DAC codes applied to AD9501 #2 and AD9501 #1 is a measure

of the settling time of the D/A converter being tested.

0.1 mF capacitor should be connected as close as possible to

each supply pin.

CLOCK IN

GROUND

00H

TRIGGER AD9501 #1

LATCH

DIGITAL

DATA

8 D/A CONVERTER

OUTPUT

UNDER TEST

RESET

V1

OUTPUT

V2

TRIGGER AD9501 #2

LATCH

DIGITAL

DATA

8

OUTPUT

RESET

LOGIC

V1

V2

OUTPUT

Figure 11. Analog Settling Time Measurement

–10–

REV. B

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