MT8910-1AP Просмотр технического описания (PDF) - Mitel Networks

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производитель

MT8910-1AP

Digital Subscriber Line Interface Circuit

Mitel Networks 

Preliminary Information

MT8910-1

Pin Description (continued)

Pin #

Name

DIP PLCC

Description

14 21 NT/LT NT/LT Mode Select. CMOS Input. When high, the DSLIC is setup in NT mode. When

low, LT mode is selected.

15 22 TSTen I/O Structure Test Enable Input. This active high input enables the built-in test of all

digital input and output structures. Refer to “I/O Structure Test" in functional description for

more details. Tie to VSS for normal operation.

16 23

SFb Superframe Pulse. In LT mode, an input pulse once every superframe (12 ms) which,

when low during a falling edge of C4b within an F0b low pulse, sets the transmit

superframe boundary.

17 25

18 27

19 30

In NT mode, a 244 ns wide output pulse once every 12 ms indicating the boundary of the

transmit superframe. In NT mode, the superframe timing is generated from the line signal

time base and, as such, SFb will only be valid once the transceiver has achieved full

activation.

C4b 4096 kHz Data Clock. In LT mode, a 4096 kHz ST-BUS clock input. In NT mode, a 4096

kHz ST-BUS clock output frequency locked to the line signal.

F0b Frame Pulse. In LT mode, an 8 kHz input pulse indicating the start of the active ST-BUS

channel times. In NT mode, an 8 kHz output pulse extracted from the line signal indicating

the start of the active ST-BUS channel times.

OSC2 Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT

mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz ±5ppm

clock (see “10.24 MHz Clock Interface" section).

20 31

When operating with a crystal (typically NT mode) connect one lead of the fundamental

mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).

OSC1 Oscillator Input. When the DSLIC operates with an External Clock (typically LT mode)

connect OSC1 to the input of an external inverter (see Fig.11).

When operating with a crystal (typically NT mode) connect the other lead of the

fundamental mode parallel resonator crystal (10.24 MHz ±50ppm in case of NT mode).

21 32 MRST Master Reset. Active low CMOS input performs a master reset of the DSLIC.

22 33

23 34

VDD Power Supply Input.

IC Internal Connection. Leave unconnected.

24 38

25 41

26 42

27 43

28 44

2,4,7,

9 -11,

17,24

26,28

29,35

36,37

39,40

AVDD

VBias

VRef

Lin-

Lin+

NC

Analog Power Supply. Connect to VDD.

Bias Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor.

Reference Voltage. Decouple to AVSS through a 1.0 µF ceramic capacitor.

Line Signal Input Minus. Internally biased at VBias.

Line Signal Input Plus. Internally biased at VBias.

No Connection. Leave circuit open.

9-5

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