TMC2242BKTC2 Просмотр технического описания (PDF) - Fairchild Semiconductor
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TMC2242BKTC2
Fairchild Semiconductor
TMC2242BKTC2 Datasheet PDF : 16 Pages
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TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Table 4b. Output Data Formats and Bit Weighting for TCO = 1
Interpolation Mode (TMC2242A and TMC2242B when INT = 0 and DEC = 1)
-21
20
2-1 … 26
2-7
2-8
2-9
2-10 2-11 2-12 2-13 2-14
Decimation, Equal Rate Modes (and TMC2242B in unity gain interpolate mode with INT = DEC = 0)
-20
2-1
2-2 … 2-7
2-8
2-9
2-10 2-11 2-12 2-13 2-14 2-15
Rounded LSBs as a function of RND2-0
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO15 SO14 SO13 …
SO8
SO8
SO8
SO8
SO8
SO8
SO8
SO8
SO7
SO7
SO7
SO7
SO7
SO7
SO7
SO7r
SO6
SO6
SO6
SO6
SO6
SO6
SO6r
0
SO5
SO5
SO5
SO5
SO5
SO5r
0
0
SO4
SO4
SO4
SO4
SO4r
0
0
0
SO3
SO3
SO3
SO3r
0
0
0
0
SO2
SO2
SO2r
0
0
0
0
0
SO1
SO1r
0
0
0
0
0
0
SO0r
0
0
0
0
0
0
0
RND2-0
000
001
010
011
100
101
110
111
Notes:
1. A leading minus sign denotes the two’s complement sign bit.
2. When TCO=0, the most significant bit of the output is positive instead of negative.
3. In all operating modes except INT = 0 and DEC = 1, the gain is approximately unity. When INT = 0 and DEC = 1, the output
gain is -6 dB.
4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to
the next lower bit, to allow the user to obtain a properly rounded output)
Table 5. TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data
Input
7FF
400
001
000
FFF
C00
801
INT = 1 or DEC = 0
TCO = 0
TCO = 1
0000 (L)
7FFF (L)
3FE7
4018
7FEF
0010
7FFF
0000
800F
FFF0
C017
BFE8
FFFF (L)
8000 (L)
INT = 0 and DEC = 1
TCO = 0
TCO = 1
3FF7 / 3FE7
4008 / 4018
5FF7 / 5FEF
2008 / 2010
7FF7
0008
7FFF
0000
8007
FFF8
A007 / A00F
DFF8 / DFF0
C007 / C017
BFF8 / BFE8
Interpretation
+ full-scale
+1/2 scale
+1 LSB
Zero
-1 LSB
-1/2 scale
- full-scale
7
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