2242AKTC2 Просмотр технического описания (PDF) - Fairchild Semiconductor

Номер в каталоге

Компоненты Описание

производитель

2242AKTC2

Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz

Fairchild Semiconductor 

PRODUCT SPECIFICATION

Description (continued)

TMC2242A/TMC2242B

The filter response is flat to within ±0.01 dB from 0.00 to

0.22 x fs, with stopband attenuation greater than 59.4 dB

from 0.28 x fs to the Nyquist frequency. The response is 6 dB

down at 0.25 x fs. Symmetric-coefficient filters such as the

TMC2242A and TMC2242B have linear phase response.

Full compliance with the CCIR-601 standard of 12 dB atten-

uation at 0.25 x fs is achieved by cascading two parts.

The TMC2242A and TMC2242B are fabricated on an

advanced submicron CMOS process. They are available in a

44-lead J-lead PLCC package. Performance is guaranteed

from 0°C to 70°C.

To perform decimation, the chip sets the output register

clock rate to half of the input rate. One output is then

obtained for every two inputs.

For interpolation, the user should bring SYNC HIGH for at

least one clock cycle, returning it LOW with the first desired

input data value. When interpolating, the chip will then con-

tinue to accept a new data input on each alternate rising edge

of the clock. When decimating, the chip will present one out-

put value for every two clock cycles. The user may leave

SYNC LOW or toggle it once per rising clock edge, with

equivalent performance.

Functional Description

The TMC2242A and TMC2242B implement a fixed-coeffi-

cient linear-phase Finite Impulse Response (FIR) filter of 55

effective taps, with special rate-matching input and output

structures to facilitate 2:1 decimation and 1:2 interpolation.

The faster of either the input or output registers will operate

at the guaranteed maximum clock rate (speed grade). The

total internal pipeline latency from the input of an impulse to

the corresponding output peak (digital group delay) is 34

cycles; the 55-value output response begins after 7 clock

cycles and ends after 61 cycles.

To perform interpolation, the chip slows the effective input

register clock rate to half the output rate. It internally inserts

zeroes between the incoming data samples to "pad" the input

data rate to match the output rate.

The output data format is two's complement if TCO is

HIGH, inverted offset binary if LOW. The user can tailor the

output data word width to his/her system requirements using

the Rounding control. As shown in Table 4, the output is

half-LSB rounded to the resolution selected by the value of

RND2-0. The asynchronous three-state output enable control

simplifies connection to a data bus with other drivers.

Table 1. Operating Modes

DEC INT TMC2242A

TMC2242B

00

Equal Rate

Interpolate (0 dB)

01

Decimate

Decimate

1 0 Interpolate (-6 dB) Interpolate (-6 dB)1

11

Equal Rate

Equal Rate

Note:

1. With 15-bit overflow protection. All other modes on both

parts limit to 16 bits.

Pin Assignments

SO12 7

SO11 8

SO10 9

SO9 10

SO8 11

GND 12

VDD 13

SO7 14

SO6 15

SO5 16

SO4 17

TMC2242A

TMC2242B

39 GND

38 VDD

37 SI10

36 SI9

35 SI8

34 SI7

33 SI6

32 SI5

31 SI4

30 SI3

29 VDD

65-2242A-02

44 Lead PLCC

2

SO12

1

SO11

2

SO10

3

SO9

4

SO8

5

GND

6

VDD

7

SO7

8

SO6

9

SO5

10

SO4

11

TMC2242A

TMC2242B

33

GND

32

VDD

31

SI10

30

SI9

29

SI8

28

SI7

27

SI6

26

SI5

25

SI4

24

SI3

23

VDD

65-2242A-02

44 Lead MQFP

Share Link: