MC100ELT25DTG(2015) Просмотр технического описания (PDF) - ON Semiconductor

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производитель

MC100ELT25DTG
(Rev.:2015)

-5 V Differential ECL to TTL Translator

ON Semiconductor 

MC10ELT25, MC100ELT25

VEE 1

D2

D3

ECL

8 VCC

TTL 7 Q

6 NC

VBB 4

5 GND

Figure 1. 8−Lead Pinout (Top View) and Logic

Diagram

Table 1. PIN DESCRIPTION

Pin

Function

D, D

ECL Differential Inputs

Q

TTL Output

VBB

VCC

VEE

GND

Reference Voltage Output

Positive Supply

Negative Supply

Ground

NC

No Connect

EP

(DFN8 only) Thermal exposed pad must be con-

nected to a sufficient thermal conduit. Electric-

ally connect to the most negative supply (GND)

or leave unconnected, floating open.

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 kW

Internal Input Pullup Resistor

N/A

ESD Protection

Human Body Model

Machine Model

> 1 kV

> 400 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Pb−Free Pkg

SOIC−8

TSSOP−8

DFN8

Level 1

Level 3

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

38 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

VCC

Positive Power Supply

GND = 0 V

VEE

Negative Power Supply

GND = 0 V

VIN

Input Voltage

GND = 0 V

IBB

VBB Sink/Source

TA

Operating Temperature Range

Tstg

Storage Temperature Range

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

VEE = −5.0 V

VCC = +5.0 V

SOIC−8

SOIC−8

7

−8

0 to VEE

± 0.5

−40 to +85

−65 to +150

190

130

V

V

V

mA

°C

°C

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

SOIC−8

TSSOP−8

TSSOP−8

41 to 44

185

140

°C/W

°C/W

°C/W

qJC

Thermal Resistance (Junction−to−Case)

Standard Board

qJA

Thermal Resistance (Junction−to−Ambient)

0 lfpm

500 lfpm

TSSOP−8

DFN8

DFN8

41 to 44 ± 5%

129

84

°C/W

°C/W

°C/W

Tsol

Wave Solder

Pb−Free <2 to 3 sec @ 260°C

265

°C

qJC

Thermal Resistance (Junction−to−Case)

(Note 2)

DFN8

35 to 40

°C/W

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

www.onsemi.com

2

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