X5043 Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

X5043

CPU Supervisor with 4K SPI EEPROM

Intersil 

Typical Application

2.7-5.0V

VCC

X5043

RESET

CS

SCK

SI

SO

WP

VSS

VCC

uC

10K

RESET

SPI

VSS

X5043, X5045

Block Diagram

VCC

CS/WDI

SI

SO

SCK

WP

+

- VTRIP

POR and Low

Voltage Reset

Generation

Reset & Watchdog

Timebase

Watchdog

Transition

Detector

Watchdog

Timer

Reset

Command

Decode &

Control

Logic

Protect Logic

Status

Register

EEPROM

Array

4Kbits

RESET (X5043)

RESET (X5045)

X5043, X5045

STANDARD VTRIP LEVEL

4.63V (+/-2.5%)

SUFFIX

-4.5A

4.38V (+/-2.5%)

-4.5

2.93V (+/-2.5%)

-2.7A

2.63V (+/-2.5%)

-2.7

See “Ordering Information” on page 3. for

more details

For Custom Settings, call Intersil.

2

FN8126.1

September 16, 2005

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