X24C04-2.7 Просмотр технического описания (PDF) - Xicor -> Intersil

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производитель

X24C04-2.7

Serial EEPROM

Xicor -> Intersil 

X24C04

Flow 1. ACK Polling Sequence

Write Operation

Completed

Enter ACK Polling

Issue

START

Issue Slave

Address and R/W = 0

ACK

NO

Returned?

YES

Next

NO

Operation

a Write?

YES

Issue Byte

Address

Issue STOP

Issue STOP

PROCEED

PROCEED

READ OPERATIONS

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the slave address is set to a one. There are three basic

read operations: current address read, random read

and sequential read.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condition

during the ninth cycle, or hold SDA HIGH during the

ninth clock cycle and then issue a stop condition.

Current Address Read

Internally the X24C04 contains an address counter

that maintains the address of the last word accessed,

incremented by one. Therefore, if the last access

(either a read or write) was to address n, the next read

operation would access data from address n + 1. Upon

receipt of the slave address with the R/W bit set to one,

the X24C04 issues an acknowledge and transmits the

eight bit word. The read operation is terminated by the

master by not responding with an acknowledge, and

issuing a stop condition. Refer to Figure 7 for the

sequence of address, acknowledge and data transfer.

Figure 7. Current Address Read

S

Bus Activity: T

Master A

Slave

Address

S

T

R

O

T

P

SDA Line S

P

Bus Activity:

X24C04

A

C

Data

K

Random Read

Random read operations allow the master to access

any memory location in a random manner. Prior to

issuing the slave address with the R/W bit set to one,

the master must first perform a “dummy” write opera-

tion. The master issues the start condition, and the

slave address followed by the word address it is to

read. After the word address acknowledge, the master

immediately reissues the start condition and the slave

address with the R/W bit set to one. This will be fol-

lowed by an acknowledge from the X24C04 and then

by the eight bit word. The read operation is terminated

by the master by not responding with an acknowledge,

and issuing a stop condition. Refer to Figure 8 for the

address, acknowledge and data transfer sequence.

REV 1.1.3 11/28/00

www.xicor.com

Characteristics subject to change without notice. 6 of 13

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