X24C01A Просмотр технического описания (PDF) - Xicor -> Intersil

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производитель

X24C01A

128 x 8 Bit Serial E2PROM

Xicor -> Intersil 

X24C01A

Sequential Read

Sequential Read can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24C01A continues to

output data for each acknowledge received. The read

operation is terminated by the master, by not responding

with an acknowledge and by issuing a stop condition.

Figure 9. Sequential Read

The data output is sequential, with the data from address

n followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing

the entire memory contents to be serially read during

one operation. At the end of the address space (address

127), the counter “rolls over” to address 0 and the

X24C01A continues to output data for each acknowl-

edge received. Refer to Figure 9 for the address, ac-

knowledge and data transfer sequence.

SLAVE

BUS ACTIVITY: ADDRESS

MASTER

SDA LINE

A

BUS ACTIVITY:

C

X24C01A

K

DATA n

A

A

A

C

C

C

K

K

K

DATA n+1

DATA n+2

S

T

O

P

P

DATA n+x

3841 FHD F14

Figure 10. Typical System Configuration

VCC

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

3841 FHD F15

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