X24645S8M Просмотр технического описания (PDF) - Xicor -> Intersil

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X24645S8M

Advanced 2-Wire Serial E2PROM with Block Lock™ Protection

Xicor -> Intersil 

X24645

READ OPERATIONS

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the slave address is set HIGH. There are three basic

read operations: current address read, random read

and sequential read.

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read op-

eration, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the

ninth clock cycle and then issue a stop condition.

Current Address Read

Internally the X24645 contains an address counter that

maintains the address of the last byte read, increment-

ed by one or the exact address of the last byte written.

Therefore, if the last access read was to address n, the

next read operation would access data from address

n + 1. Upon receipt of the slave address with the R/W

set HIGH, the X24645 issues an acknowledge and

transmits the byte. The read operation is terminated by

the master; by not responding with an acknowledge

and by issuing a stop condition. Refer to Figure 7 for the

sequence of address, acknowledge and data transfer.

Random Read

Random read operations allow the master to access

any memory location in a random manner. Prior to issu-

ing the slave address with the R/W bit set HIGH, the

master must first perform a “dummy” write operation.

The master issues the start condition, and the slave ad-

dress with the R/W bit set LOW, followed by the byte

address it is to read. After the word address acknowl-

edge, the master immediately reissues the start condi-

tion and the slave address with the R/W bit set HIGH.

This will be followed by an acknowledge from the

X24645 and then by the data byte. The read operation

is terminated by the master; by not responding with an

acknowledge and by issuing a stop condition. Refer to

Figure 8 for the address, acknowledge and data trans-

fer sequence.

Figure 7. Current Address Read

S

BUS ACTIVITY:

MASTER

T

A

R

SLAVE

ADDRESS

T

SDA LINE

S

A

BUS ACTIVITY:

C

X24645

K

S

T

O

P

P

DATA

2783 ILL F11

Figure 8. Random Read

BUS ACTIVITY:

MASTER

S

T

A

R

SLAVE

ADDRESS

T

BYTE

ADDRESS n

S

T

A

R

SLAVE

ADDRESS

T

SDA LINE

S

S

BUS ACTIVITY:

X24645

A

A

A

C

C

C

K

K

K

S

T

O

P

P

DATA n

2783 ILL F12.1

7

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