TDA7535 Просмотр технического описания (PDF) - STMicroelectronics
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TDA7535 Datasheet PDF : 12 Pages
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TDA7535
3
I2S interface
I2S interface
Figure 3. I2S interface diagram
Left
FSYNC
Right
32 * SCK
32 * SCK
SCK
SDATA
20 Bits
20 Bits
uct(s) MSB
LSB
MSB
LSB
Prod Figure 4. I2S timings
lete SDATA
Valid
so FSYNC
roduct(s) - Ob SCK
tsckr
Valid
tsckf
tlrw- tlrw+
tsds
tsckpl
tsdh
tsckph
tsck
lete P Table 10. Timing characteristics
o Timing
Description
Obstsck Clock cycle(1)
Min.
Max.
Unit
1/(64*Fs) - 150psRMS 1/(64*Fs) + 150psRMS ns
tsckpl SCK phase low
0.5*tsck - 1%
0.5*tsck +1%
ns
tsckph SCK phase high
0.5*tsck - 1%
0.5*tsck +1%
ns
tlrw-
FSYNC switching time window before SCK falling
edge(2)
0
0.125*tsck-10
ns
tlrw+
FSYNC switching time window after SCK falling
edge(2))
0
0.125*tsck-10
ns
tsds SDATA setup time
tsdh SDATA hold time
60
ns
30
ns
7/12
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