Pre Production
WM8952
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD=1.8V, AVDD=3.3V, DGND=AGND=0V, TA = +25oC
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
Note 1:
SYMBOL
CONDITIONS
MIN
TMCLKY
TMCLKDS
MCLK=SYSCLK (=256fs)
MCLK input to PLL Note 1
81.38
20
60:40
TYP
MAX
40:60
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
UNIT
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
w
PP, Rev 3.1, June 2011
11