WM8974 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8974

MONO CODEC WITH SPEAKER DRIVER

Wolfson Microelectronics plc 

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SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8974

Figure 1 System Clock Timing Requirements

Test Conditions

DCVDD=1.62V, DBVDD=AVDD=SPKRVDD=3.3V, DGND=AGND=SPKRGND=0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK =

256fs, 24-bit data, unless otherwise stated.

PARAMETER

System Clock Timing Information

MCLK System clock cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

MIN

Tbd

60:40

TYP

MAX

40:60

UNIT

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

w

PP Rev 1.1 September 2004

9

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