WM8974 Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8974 Datasheet PDF : 63 Pages
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WM8974
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Test Conditions
DCVDD=1.62V, DBVDD=AVDD=SPKRVDD=3.3V,
MCLK=256fs, 24-bit data, unless otherwise stated.
DGND=AGND=SPKRGND=0V,
TA=+25oC,
Slave
Mode,
fs=48kHz,
PARAMETER
Audio Data Input Timing Information
FRAME propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
SYMBOL
tDL
tDDA
tDST
tDHT
MIN
10
10
TYP
MAX
UNIT
10
ns
10
ns
ns
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.62V, DBVDD=AVDD=SPKRVDD=3.3V, DGND=AGND=SPKRGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=
256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
FRAME set-up time to BCLK rising edge
FRAME hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
Note:
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDD
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
BCLK period should always be greater than or equal to MCLK period.
w
PP Rev 1.1 September 2004
10
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