WM9709CDS Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM9709CDS Datasheet PDF : 18 Pages
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WM9709
DEVICE DESCRIPTION
INTRODUCTION
WM9709 contains a minimal subset of a revision 1.03 AC’97 compliant audio codec.
WM9709 comprises a stereo 20-bit DAC and an Intel revision 1.03 AC-link compatible interface. No
internal volume control stages, mute function or power down registers are provided. Vendor ID data
may be read back from registers 7C and 7E. The SDATAIN output pin is used for outputting digital
signals during manufacturing test, but does not output signals in normal operation.
The DACs on WM9709 are implemented using a multi-bit switched capacitor sigma delta
architecture which gives inherently low out of band noise and reduced clock jitter sensitivity.
An internally generated mid-rail reference is provided at pin CAP which is used as the chip
reference. This pin should be heavily de-coupled. See Figure 11.
CONTROL AND DATA INTERFACE
A digital interface to control and transfer to and from the WM9709 has been provided. This serial
interface is compatible with the Intel revision 1.03 AC-link specification.
The main control interface functions are:
• Transfer of DAC words from AC-link controller.
• Control of test modes.
• Readback of vendor ID.
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
WM9709 incorporates a 5 pin digital serial interface that links it to the AC-link controller. The AC-link
is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio
streams, as well as control register accesses employing a time division multiplexed (TDM) scheme.
The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams,
each with 20-bit sample resolution. WM9709 provides support for up to 20-bit operation of outgoing
DAC data only. No incoming data is provided other than readback of vendor ID. A read request to
any address other than 7C or 7E will respond with all 0s.
SLOT #
0
1
2
3
4
5
6
7
8
9
10 11 12
SYNC
OUTGOING
STREAMS
INCOMING
STREAMS
TAG PHASE
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RIGHT
OPT
MDM CDC
CENTR
ER
LSURR
RSURR LFE
RSRVD RSRVD RSRVD
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
PCM
RIGHT
OPT
MDM CDC
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
DATA PHASE
Figure 8 AC-link Standard Bi-directional Audio Frame
Synchronisation of all AC-link data transactions is signaled by the WM9709 controller. When
WM9709 operates as a master (ID = ‘lo’, normal operation) WM9709 drives the serial bit clock
BITCLK onto the AC-link, which the AC-link controller then qualifies with a synchronisation signal to
construct audio frames. When a multi channel system is implemented using 2 or 3 WM9709 or other
AC’97 devices, one of the AC link devices MUST be a master. Other WM9709 devices used as
surround or centre/LFE channel devices (by selecting ID = high or ‘Z’) act as slaves. In this case
BITCLK is an input. The system clock is not required for slave devices, which use BITCLK for all
internal functions. The BITCLK input is used for all internal filtering operations.
w
PD Rev 1.3 February 2003
9
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