WM8773 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8773

24-bit, 96kHz ADC with 8 Channel I/P Multiplexer

Wolfson Microelectronics plc 

WM8773

MASTER CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

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Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

System Clock Timing Information

MCLK System clock pulse width high

tMCLKH

MCLK System clock pulse width low

tMCLKL

MCLK System clock cycle time

tMCLKY

MCLK Duty cycle

TEST CONDITIONS

MIN

11

11

28

40:60

TYP

MAX

UNIT

ns

ns

ns

60:40

Table 1 Master Clock Timing Requirements

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

WM8773

ADC ADCLRC

DOUT

DSP/

ENCODER/

DECODER

Figure 2 Audio Interface - Master Mode

PP Rev 1.0 June 2002

8

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