WM8771IFT Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8771IFT Datasheet PDF : 44 Pages
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WM8771
DIGITAL AUDIO INTERFACE – SLAVE MODE
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BCLK
ADCLRC
WM8771
CODEC DACLRC
DOUT
DIN1/2/3/4
4
DSP
ENCODER/
DECODER
Figure 4 Audio Interface – Slave Mode
BCLK
DACLRC/
ADCLRC
DIN1/2/3/4
DOUT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tBCY
tBCH
tBCL
tLRSU
DACLRC/ADCLRC hold
tLRH
time from BCLK rising edge
DIN1/2/3/4 set-up time to
tDS
BCLK rising edge
DIN1/2/3/4 hold time from
tDH
BCLK rising edge
DOUT propagation delay
tDD
from BCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
50
20
20
10
10
10
10
0
10
Table 3 Digital Audio Data Timing – Slave Mode
Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8771 interface is tolerant of phase variations or jitter on these signals.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
w
PP Rev 2.0 December 2001
10
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