WM8740EDS Просмотр технического описания (PDF) - Wolfson Microelectronics plc
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WM8740EDS Datasheet PDF : 24 Pages
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WM8740
NORMAL SAMPLE RATE
Production Data
In normal mode, the data is input serially on one pin for both left and right channels.
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word
length) that were clocked in prior to the transition on LRCIN are valid.
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in
as the first 20 or 24 bits after a transition on LRCIN.
For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified”
except with one additional preceding clock cycle.
LRCIN (PIN 1)
LEFT
1/fs
RIGHT
BCKIN (PIN 3)
16-BIT RIGHT
JUSTIFIED B2 B1 B0
DIN (PIN 2)
B15
B2 B1 B0
B15
B2 B1 B0
20-BIT RIGHT
JUSTIFIED B2 B1 B0
DIN (PIN 2)
B19 B18 B17
B2 B1 B0
B19 B18 B17
B2 B1 B0
24-BIT RIGHT
JUSTIFIED B2 B1 B0
DIN (PIN 2)
B23 B22 B21 B20 B19
B2 B1 B0
B23 B22 B21 B20 B19
B2 B1 B0
24-BIT LEFT
JUSTIFIED B0
DIN (PIN 2)
B23 B22 B21
B4 B3 B2 B1 B0
B23 B22 B21
B4 B3 B2 B1 B0
20-BIT LEFT
JUSTIFIED B0
DIN (PIN 2)
B19 B18 B17
B0
B19 B18 B17
B0
LRCIN (PIN 1)
LEFT
RIGHT
BCKIN (PIN 3)
16-BIT I2S
DIN (PIN 2)
24-BIT I2S
DIN (PIN 2)
20-BIT I2S
DIN (PIN 2)
B15
B2 B1 B0
B15
B2 B1 B0
B15
B23
B6 B5 B4 B3 B2 B1 B0
B23
B6 B5 B4 B3 B2 B1 B0
B23
B19
B2 B1 B0
B19
B2 B1 B0
B19
Figure 4 Audio Data Input Format
w
PD Rev 4.0 April 2004
10
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