WM8734 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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Компоненты Описание

производитель

WM8734

Stereo Audio CODEC

Wolfson Microelectronics plc 

WM8734

MASTER CLOCK TIMING

MCLK

t MCLKL

t MCLKH

t MCLKY

Production Data

Figure 1 System Clock Timing Requirements

Test Conditions

AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless

otherwise stated.

PARAMETER

SYMBOL

System Clock Timing Information

MCLK System clock pulse width high

TXTIH

MCLK System clock pulse width low

TXTIL

MCLK System clock cycle time

TXTIY

MCLK Duty cycle

TEST CONDITIONS

MIN

18

18

54

40:60

TYP

MAX

UNIT

ns

ns

ns

60:40

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

ADCLRC

WM8734

CODEC DACLRC

ADCDAT

DACDAT

DSP

ENCODER/

DECODER

Figure 2 Master Mode Connection

w

PD Rev 4.1 November 2006

11

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