WM8143-12 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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WM8143-12

12-bit/4MSPS CCD Signal Processor

Wolfson Microelectronics plc 

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WM8143-12

Device Description

The WM8143-12 is configured to output 12-bit data by

writing to Set-up Register 4: Bit4 (Mode12). By default

the device is configured to output 10 bit data.

The Programmable Gain Amplifier block multiplies the

resulting input voltage by a value between 0.5 and 8.25

which can be programmed independently for each of

the three input channels via the serial (or parallel)

interface.

S/H, Offset DACs and PGA

Each analogue input (RINP, GINP, BINP) of the

WM8143-12 consists of a sample and hold, a

programmable gain amplifier, and a DC offset

correction block. The operation of the red input stage is

summarised in Figure 2.

RINP

S/H

VS

VMID

S/H

RS

+

GAIN=G

-

+

+

VADC

VOFFSET

VMID

Figure 2 Operation of Red Input Stage

The sample/hold block can operate in two modes of

operation, CDS (Correlated Double Sampling) or Single

Ended.

In CDS operation the video signal processed is the

difference between the voltage applied at the RINP

input when RS occurs, and the voltage at the RINP

input when VS occurs. This is summarised in Figure 3.

VRS

Table 1 illustrates the PGA Gains Register codes

required for typical gains (see Typical Performance

Graphs). The typical gain may also be calculated using

the following equation:

Typical Gain = 0.5+(Code ∗ 0.25).

CODE

00000

TYPICAL

GAIN

0.5

CODE

10000

TYPICAL

GAIN

4.5

00001 0.75

10001 4.75

00010 1

10010 5.0

00011 1.25

10011 5.25

00100 1.5

10100 5.5

00101 1.75

10101 5.75

00110 2.0

10110 6.0

00111 2.25

10111 6.25

01000 2.5

11000 6.5

01001 2.75

11001 6.75

01010 3.0

11010 7.0

VVS

RS

VS

Figure 3 Video Signal Processed in CDS Mode

When using CDS the actual DC value of the input

signal is not important, as long as the signal extremes

are maintained within 0.5 volts of the chip power

supplies. This is because the signal processed is the

difference between the two sample voltages, with the

common DC voltage being rejected.

In Single Ended operation, the VS and RS control

signals occur simultaneously, and the voltage applied

to the reset switch is fixed at VMID. This means that the

voltage processed is the difference between the voltage

applied to RINP when VS/RS occurs, and VMID. When

using Single Ended operation the DC content of the

video signal is not rejected.

01011 3.25

01100 3.5

01101 3.75

01110 4.0

01111 4.25

11011 7.25

11100 7.5

11101 7.25

11110 8.0

11111 8.25

Table 1 Typical Gain

The DC value of the gained signal can then be trimmed

by the 8 bit plus sign DAC. The voltage output by this

DAC is shown as VOFFSET in Figure 2. The range of the

DAC is (VMID/2) or 1.5∗(VMID/2) if the DAC_RANGE bit

in Setup Register 4 is set.

The output from the offset DAC stage is referenced to

the VMID voltage. This allows the input to the ADC to

maximise the dynamic range, and is shown

diagrammatically in Figure 2 by the final VMID addition.

Wolfson Microelectronics

PD. Rev 4 Nov. 99

9

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