WM2632 Просмотр технического описания (PDF) - Wolfson Microelectronics plc

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производитель

WM2632

Octal 8-bit, Serial Input, Voltage Output DAC with Internal Reference

Wolfson Microelectronics plc 

Production Data

WM2632

Test Characteristics:

RL = 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over

recommended operating free-air temperature range (unless noted otherwise).

PARAMETER

Reference Configured as Input

SYMBOL

TEST

CONDITIONS

MIN TYP

MAX UNIT

Reference input resistance

RREF

50

kΩ

Reference input capacitance

CREF

10

pF

Reference feedthrough

Reference input bandwidth

Reference Configured as Output

VREF=2VPP at 1kHz

-84

+ 2.048V DC, DAC code 0

VREF= 0.4VPP + 2.048V DC,

DAC code 128

Slow

1.9

Fast

2.2

dB

MHz

MHz

Low reference voltage

VREFOUTL

1.010 1.024 1.040

V

High reference voltage

VREFOUTH

VDD > 4.75V

2.020 2.048 2.096

V

Output source current

IREFSRC

1

mA

Output sink current

IREFSNK

-1

mA

Load Capacitance

in parallel with 100nF cap.

1

10

µF

PSRR

60

dB

Digital Inputs

High level input current

IIH

Input voltage = DVDD

-1

1

µA

Low level input current

IIL

Input voltage = 0V

-1

1

µA

Input capacitance

CI

8

pF

Notes:

1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding

the effects of zero code and full scale errors).

2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change

of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same

direction (or remains constant) as a change in digital input code.

3. Zero code error is the voltage output when the DAC input code is zero.

4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.

5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the

proportion of this signal imposed on the zero code error and the gain error.

6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.

7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ

load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.

8. IDD is measured while continuously writing a digital code of 128 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V

supply current will increase.

9. Slew rate results are for the lower value of the rising and falling edge slew rates.

10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and

falling edges. Limits are ensured by design and characterisation, but are not production tested.

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 April 2001

5

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