WED2ZLRSP01S Просмотр технического описания (PDF) - White Electronic Designs Corporation

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WED2ZLRSP01S

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

White Electronic Designs Corporation 

White Electronic Designs

WED2ZLRSP01S

FIG. 6 TIMING WAVEFORM OF CKE# OPERATION

Clock

CKE#

tCES tCEH

Address

A1

A2

A3

WRITE#

CEx#

ADV

OE#

Data Out

Data In

tCD

tLZC

tHZC

Q1

NOTES:

WRITE# = L means WE# = L, and BWx# = L

CEx# refers to the combination of CE1#, CE2 and CE2#.

Note:

Applies to both independent arrays.

tCH tCL

tCYC

A4

A5

A6

Q3

tDS

tDH

D2

Q4

Dont Care

Undefined

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

April, 2002

Rev. 0

11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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