WED2ZLRSP01S Просмотр технического описания (PDF) - White Electronic Designs Corporation

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WED2ZLRSP01S

512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM

White Electronic Designs Corporation 

White Electronic Designs

WED2ZLRSP01S

FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE

Clock

CKE#

tCES tCEH

Address

A1

A2

A3

A4

A5

A6

A7

WRITE#

CEx#

ADV

OE#

Data In

Data Out

tOE

tLZOE

Q1

Q2

tDS

tDH

D2

Q4

D5

NOTES:

WRITE# = L means WE# = L, and BWx# = L

CEx# refers to the combination of CE1#, CE2 and CE2#.

Note:

Applies to both independent arrays.

tCH tCL

tCYC

A8

A9

Q6

Q7

Dont Care

Undefined

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

April, 2002

Rev. 0

10

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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