W9816G6CH Просмотр технического описания (PDF) - Winbond
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W9816G6CH Datasheet PDF : 43 Pages
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W9816G6CH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
20−24,
27−32
19
A0−A10
BA
Address
Bank Select
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
Select bank to activate during row address latch time,
or bank to read/write during column address latch
time.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
DQ0−DQ15
Data Input/
Output
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
18
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
17
Row Address
RAS
Strobe
the clock, RAS , CAS and WE define the operation
to be executed.
16
Column
CAS
Address Strobe Referred to RAS
15
36, 14
35
34
1, 25
26, 50
7, 13, 38, 44,
4, 10, 41, 47
33, 37
WE
UDQM/
LDQM
CLK
CKE
VCC
VSS
VCCQ
VSSQ
NC
Write Enable Referred to RAS
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power (+3.3V) Separated power from VCC, used for output buffers to
for I/O buffer improve noise immunity.
Ground for I/O Separated ground from VSS, used for output buffers
buffer
to improve noise immunity.
No Connection
No connection. (NC pin should be connected to GND
or floating)
Publication Release Date: June 10, 2005
-5-
Revision A0
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